Strange warning message from ise8.2i ?

Waiting might not do anything for you. Do you want help?

There's a chance that your logic is not doing what you expect. Have you run this through simulation software? My guess - if you do - is that the signal will always be ground because the logic reduces to always-zero output.

Hello, Here is my program, if you want to compile it and see for yourself, it would be wonderful. Waiting with antissipation, Thanks.

module vv(clk1, clk2, reset1,reset2, addr1); input clk1; input clk2; input reset1; input reset2; output [4:0] addr1; wire [4:0] addr1; wire int_mux_clk; wire int_done; mmux mymux(.a(clk1),.b(clk2),.sel(int_done),.y(int_mux_clk)); mcounter mycounter(.clk(int_mux_clk),.rs(reset1),.ad(addr1)); mdetect mydetect(.a(addr1[4]),.rs(reset2),.y(int_done)); endmodule

module mmux(a,b,sel,y); input a, b, sel; output y; reg y; always @ (a or b) begin if (sel==0) y=a; else y=b; end endmodule

module mcounter (clk,rs,ad); input clk,rs; output [4:0] ad; reg [4:0] ad; always @ (posedge clk or posedge rs) begin if(rs) ad=0; else ad=ad+1; end endmodule

module mdetect(a,rs,y); input a; input rs; output y; reg y; always @(a or rs) begin if (a) y=1; else if(rs) y=0; else y=y; end endmodule

Since you have no signal or module named "done" and I wouldn't expect the tools to rename your int_done wire, are you sure this code generated the "error warning" (please specify if it's an error or a warning) that done.RSTF was minimized to ground?

Also, the word is "anticipation" just for your information, no offense.

Here are all the warnings generated. If you compile it you will see the same:

WARNING:Xst:905 - "vv.v" line 22: The signals are missing in the sensitivity list of always block. WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:1355 - Unit mmux is merged (low complexity) WARNING:Cpld:828 - Signal 'int_done.SETF' has been minimized to 'GND'. WARNING:Cpld:310 - Cannot apply TIMESPEC TS1000 =

The first one I know how to fix. The 2nd one, I assume it's because of the bus bit associated with it, so ok.

3rd one, stange, but ok, I have no objections. 4th one, SETF, what is that ? Last one, TIMESPEC ?

Waiting with anticipation Thanks.

If you fix the problem for y (in mdetect which drives int_done) your int_done warning will probably go away. The SETF is probably a control pin for the latch element that XST was trying to produce for you. As it tried to contort your intent into a latch, I'm guessing it generated a set signal that - in the end - wasn't needed.

By the way, I can only compile and get the same results if I have ISE8.2i (of unknown service pack) and know what CPLD family you're targeting. Since I'm up to ISE9.1i+, I won't bother.

Good code produces few warnings.