Hi Folks,
For educational purpose (Von Neumann demo), I am looking for a System On Chip Processor :
- very simple
- gate level design (no VHDL, only gates AND,NAND, and low level boxes as shifter, ...)
- running system (spartan 3 or other low cost xilinx or altera demo board)
regards Raph
"raph" schrieb im Newsbeitrag news:435ca17a$0$20868$ snipped-for-privacy@news.free.fr...
there is no such thing, not directly.
some OOOLD desing may have been done on the level you wish, but none of those designs has been ported to any modern FPGA as S-3.
what means you are stick to use VHDL code - BTW Xilinx picoblaze is pretty low level already, still being in VHDL
and... a shifter is not generically a low level box. low level primitives are LUT and FF, pretty much everthing else is higher level already. xilinx SRL16 od low level shiftrt but is in xilinx only. there is no vendor neutral low level box as shifter (shift register).
so if you need basic gates only then you need to translate some HDL code into the primitives...
antti
The second one is quite an ask.... I'd suggest you look at the Mico8 core from Lattice, which is open source & can run on their MachXO devices.
You can then a) recode the HDL, so it 'reads' to the students as lower level. b) rewrite the HDL in ABEL, which is more direct HW mapping ( but is less portable - IIRC Lattice and Xilinx still have Abel, & unclear if that is more than CPLD only tool flow )
Xilinx Abel flows, last time I checked, also output a low level VHDL, which can also be used for teaching/and or learning how to write low level HDL :)
-jg
Once you synthesize you vhdl/verilog coded processor, view the rtl schematic or technology schematic. That will give you a good enough representation of the HDL in basic blocks / Xilinx primitives. If you double click on a single LUT in the technology schematic, it'll give you a gate implementation representation, k-map, and truth table. RTL schematic / technology schematic can be viewed by double clicking the 'view RTL schematic' / 'view technology schematic' in the process window in ISE. The schematic can be difficult to trace for larger designs. Synplicity gives more readable schematics.
Kunal
you are an idiot !
No one in their right mind would design a processor like that with an implementation goal of putting it in a FPGA.
Simon
Well, no AND or NAND but perhaps close enough for government work.
-- rk, Just an OldEngineer "These are highly complicated pieces of equipment almost as complicated as living organisms. In some cases, they've been designed by other computers. We don't know exactly how they work." -- Scientist in Michael Crichton's 1973 movie, Westworld
And the guy built one in his basement! Took him four years.
I'm reminded of Wallace and Gromit's Grand Day Out.
Personally I'd like to convert the design to VHDL so I can have one running in a single FPGA.
The 3-input NOR gates are simple, but a glance at the circuits shows many other types of circuits involving small pulse transformers etc. Many of the gates are used to make asynchronous cross-coupled SR latches and I suspect those may not suit the generally synchronous nature of FPGA chips.
It may be better to devise functional block equivalents rather than trying to copy the low-level design.
Oh well, if someone has more time than I do...
:-)
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