Where I work, we aren't allowed to directly connect FPGA or CPLD pins directly to external connectors, save for on-board test points (like Mictor connectors). Everything goes through external buffers or registers. Yes, it does add latency, but it does protect hard-to-replace BGA's from damage.
Of course, I work on military hardware, and reliability is a major factor. While most things are replaced at LRU (chassis) level, there are some systems where the customer is allowed to replace individual boards. Usually, this happens in a customer repair facility, and is done by military technicians, but still - it pays to go the extra mile.
The other factor is that every board costs so much, that they are almost never thrown away, and instead reworked. It is much simpler to replace a buffer chip than a BGA.
It is more expensive, but if you are worried about damaging boards with ESD or want to hot-slot safely, it's worth it.
BTW - we use SRAM based FPGA's for everything except space applications. There, we use fusible-link devices from Actel or ASICs. A typical system will load dynamically over VME or PCI from a host controller, rather than local configuration memories - but that really shouldn't be a factor. (we do it to simplify inventory issues where a board may be sold to different customers)
We do occasionally need a PAL or CPLD to implement something that just needs to be off-chip. A good example is controlling the PCI/VME based FPGA configuration process. (specifically, we use them as SVF players) We generally use flash-based devices for that, since they generally only need to be updated once - and speed isn't usually a concern.
As far as I can tell, the SRAM FPGA's have been working just fine across a very wide spectrum of environmental conditions for a long time. Their reliability is actually quite good.