Re: Enhancing PAR with FPGA floorplanners

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As far as cost goes, it again comes down to what you are trying to achieve.
Many times, the cost of the tools could be justified easily by showing the
savings - for example, saving a speedgrade (use a slower speedgrade part) by
the use of physical synthesis has a great impact on the total cost of your
board.

Using placement constraints is okay if you are trying to meet timing on
certain small sections of the designs AND you know if these are going to be
the bottleneck. It is not feasible to do this if you have a big design that
is using 90+% of the slices/LEs etc.

As FPGAs are getting bigger and can accomodate complex designs, there are
newer physical synthesis tools in the market that have different approaches
to solving the timing closure issue. It is definitely worthwhile to check
them out.


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Re: Enhancing PAR with FPGA floorplanners
 
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Ray's impressive designs are mostly regular structures, mostly data
path.  Placement in the bottom levels of code works well for such
designs.  When the critical paths are in complex control logic, such
placement isn't a realistic alternative.  Other techniques are more
useful.  FPGA designs are not all the same sorts of things.  Different
requirements lead to different usages of the parts and the tools.


--
Phil Hays

Re: Enhancing PAR with FPGA floorplanners

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However, the complex-control-logic hairballs are what simulated
annealing and related FPGA placement algorithms are designed to do
best.  A common (and effective) technique is to hand-place the regular
datapath, and then let the placement tool arrange the control logic
around the periphery.
--
Nicholas C. Weaver                                 snipped-for-privacy@cs.berkeley.edu

Re: Enhancing PAR with FPGA floorplanners
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How good is the current software?

Many years ago, I could, do a manual placement and automatic routing
if far less time than the P&R tools took to do the whole job.

My "complex-control-logic hairballs" were generally pretty simple,
mostly one-hot state machines.  Maybe some pipelining to help.
(They probably have to be simple if you are going to co-exist with
a well planned data path.)

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Re: Enhancing PAR with FPGA floorplanners
Ray,
What I have in mind is mid complexity designs that would benefit from some sort
of automated flow to produce a better placement to fit into smaller or lower
speed grade devices, as the vendors promise.

I understand that most high end designers will be doing floorplanning and
constraining themselves, using on other tools, like formal verification, as they
make progress.

But what I would like to know is what are the features to look for in a 3rd
party floorplanner to make it worth it. If someone with average design
experience, wanted to use one of this tools to stitch IP/blocs or to make
modifications to other's designs (for an ECO, for example) what should I be
looking for?

I have also looked at hierarchical methodologies, but it only works if
implemented form the start. My testcases are large flat design that I've hacked.
I've found it difficult to partition these designs and make the changes to the
constraints to still meet timing. Most of these design had very narrow timing
margins and/or were almost full. For me, this is were one of these tool might
help. But I would appreciate input form this newsgroup.

Cheers,

***
Alfredo.


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