Modelsim report is:
# Reading C:/Modeltech_6.1b/tcl/vsim/pref.tcl # // ModelSim SE 6.1b Sep 8 2005 # // # // Copyright Mentor Graphics Corporation 2005 # // All Rights Reserved. # // # // THIS WORK CONTAINS TRADE SECRET AND # // PROPRIETARY INFORMATION WHICH IS THE PROPERTY # // OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS # // AND IS SUBJECT TO LICENSE TERMS. # // # do {test_clock.fdo} # ** Warning: (vlib-34) Library already exists at "work". # Model Technology ModelSim SE vlog 6.1b Compiler 2005.09 Sep 8 2005 # -- Compiling module stm4ser # # Top level modules: # stm4ser # Model Technology ModelSim SE vlog 6.1b Compiler 2005.09 Sep 8 2005 # -- Compiling module dcm1 # # Top level modules: # dcm1 # Model Technology ModelSim SE vlog 6.1b Compiler 2005.09 Sep 8 2005 # -- Compiling module clock # # Top level modules: # clock # Model Technology ModelSim SE vlog 6.1b Compiler 2005.09 Sep 8 2005 # -- Compiling module test_clock # # Top level modules: # test_clock # Model Technology ModelSim SE vlog 6.1b Compiler 2005.09 Sep 8 2005 # -- Compiling module glbl # # Top level modules: # glbl # vsim -L xilinxcorelib_ver -L unisims_ver -lib work -t 1ps test_clock glbl # Loading work.test_clock # Loading work.clock # Loading work.dcm1 # Loading C:\Xilinx\verilog\mti_se\unisims_ver.BUFG # Loading C:\Xilinx\verilog\mti_se\unisims_ver.IBUFG # Loading C:\Xilinx\verilog\mti_se\unisims_ver.DCM # Loading C:\Xilinx\verilog\mti_se\unisims_ver.dcm_clock_divide_by_2 # Loading C:\Xilinx\verilog\mti_se\unisims_ver.dcm_maximum_period_check # Loading C:\Xilinx\verilog\mti_se\unisims_ver.dcm_clock_lost # Loading work.stm4ser # Loading C:\Xilinx\verilog\mti_se\unisims_ver.GT_CUSTOM # Loading C:\Xilinx\verilog\mti_se\unisims_ver.GT # Loading C:\Xilinx\verilog\mti_se\unisims_ver.GT_SWIFT # Loading C:\Xilinx\verilog\mti_se\unisims_ver.GT_SWIFT_BIT # Loading work.glbl # ** Warning: (vsim-PLI-3003) C:/Xilinx/verilog/mti_se/unisims_ver/unisims_ver_SmartWrapper_source.v(18339): [TOFD] - System task or function '$lm_model' is not defined. # Region: /test_clock/UUT/module1/GT_CUSTOM_INST/gt_1/gt_swift_1/I1 # .main_pane.mdi.interior.cs.vm.paneset.cli_0.wf.clip.cs.pw.wf # .main_pane.workspace # .main_pane.signals.interior.cs # No errors or warnings. # Break at test_clock.tfw line 82 # Simulation Breakpoint: Break at test_clock.tfw line 82 # MACRO ./test_clock.fdo PAUSED at line 17
In this report I'm not andestend warning. All off signals from RocketIO module is x-state. But all of oter modules simulate succes.
:) And sorry my very bad english