ML403 board - VGA schematics - wrong pins

Hi, namesake,

On the ML403, some VGA pins are missing, IIRC there are only 5 bits per colour. On the ML402, these pins are available. The epoxy board seems to be the same. (I have ML402s only)

The 3 bits are not much of a loss, because the analog quality of the DAC outputs is so sh***y that you will never see pretty eye diagrams etc if you use them as pseudo-analog test points for your DSP stuff (clock feedthru, overshoot...) That hurts, because the ML402 is meant for DSP.

BTW, will the Webpack 9.1 recognize a valid full ISE 8.1 installation and work for the V4-SX35 on the ML402? (interim solution until the CDs are here)

regards, Gerhard

Hi Gerardo Sosa

I switch from ML402 to ML403 and back quite often. The ML403 give me faster compile times so it's good for testing small designs. When I do this I comment the extra pins out as shown in the UCF file below.

I also have to change my VHDL to reflect fewer inputs with the ML403 and I am searching for a way to automate that procedure.

It seems like I don't use the blank, sync_n, or p_save pins in either design. Just HSYNC VSYNC and CLK. They must be pulled to acceptable levels.

Brad Smallridge AiVision

# VGA OUTPUTS

NET "vga_clk_out" LOC = "AF8" ; NET "vga_clk_out" IOSTANDARD = LVDCI_33 ; NET "vga_clk_out" SLEW = FAST ; NET "vga_clk_out" DRIVE = 8 ;

NET "vga_vsync_out" LOC = "A8" ; NET "vga_vsync_out" SLEW = FAST ; NET "vga_vsync_out" DRIVE = 8 ;

NET "vga_hsync_out" LOC = "C10" ; NET "vga_hsync_out" SLEW = FAST ; NET "vga_hsync_out" DRIVE = 8 ;

NET "vga_b_out" LOC = "C5" ; # VGA_B3 or tft_lcd_b NET "vga_b_out" LOC = "C7" ; # VGA_B4 or tft_lcd_b NET "vga_b_out" LOC = "B7" ; # VGA_B5 or tft_lcd_b NET "vga_b_out" LOC = "G8" ; # VGA_B6 or tft_lcd_b NET "vga_b_out" LOC = "F8" ; # VGA_B7 or tft_lcd_b #NET vga_b_out IOSTANDARD = LVCMOS33; NET "vga_g_out" LOC = "E4" ; # VGA_G3 or tft_lcd_g NET "vga_g_out" LOC = "D3" ; # VGA_G4 or tft_lcd_g NET "vga_g_out" LOC = "H7" ; # VGA_G5 or tft_lcd_g NET "vga_g_out" LOC = "H8" ; # VGA_G6 or tft_lcd_g NET "vga_g_out" LOC = "C1" ; # VGA_G7 or tft_lcd_g #NET vga_g_out IOSTANDARD = LVCMOS33; NET "vga_r_out" LOC = "C2" ; #VGA_R3 tft_lcd_r NET "vga_r_out" LOC = "G7" ; #VGA_R4 tft_lcd_r NET "vga_r_out" LOC = "F7" ; #VGA_R5 tft_lcd_r NET "vga_r_out" LOC = "E5" ; #VGA_R6 tft_lcd_r NET "vga_r_out" LOC = "E6" ; #VGA_R7 tft_lcd_r

# extra VGA connections for ML402 not ML403 #NET vga_b_out LOC = "M26"; #NET vga_b_out LOC = "M21"; #NET vga_b_out LOC = "L26"; #NET vga_g_out LOC = "M22"; #NET vga_g_out LOC = "M23"; #NET vga_g_out LOC = "M20"; #NET vga_r_out LOC = "N23"; #NET vga_r_out LOC = "N24"; #NET vga_r_out LOC = "N25"; # END EXTRA CONNECTIONS

#NET vga_psave_n LOC = "M25"; #NET vga_blank_n LOC = "M24"; #NET vga_sync_n LOC = "L23";

# drive strength and speed for VGA NET vga_r_out SLEW = FAST; NET vga_r_out DRIVE = 8; NET vga_g_out SLEW = FAST; NET vga_g_out DRIVE = 8; NET vga_b_out SLEW = FAST; NET vga_b_out DRIVE = 8;

Thanks por the advice, I'm going to modify my ADV7125 driver to work with HSYNC VSYNC and CLK signals only.

Regards

Gerardo

Thanks Brad...It's works!!!

I removed the code for Blank and Sync lines and force the rgb channels to black in the front porch, sync pulse and back porch.

In my original driver it's no matter the data in rgb channels, because Blank and sync lines force the blanking.

Thank you very much for the advice, I solved in less than five minutes.

Regards

Gerardo Sosa

I use ML405 did same things for my board but there is not success, can you explain what are these things means , may be i need to change something to adopt to my board ?

That post is nearly 9 years old, so he has probably forgotten by now.

-- Brian

Yep ))))