Hello,
I am following the new (Jan 12 '04) ML300 EDK user guide to build, simulate, and run a reference design from the EDK
I have no problem building and running the reference design (system_hello_uart) on the ML300, but simulation will not work. I have tried ModelSim SE 5.7 and 5.8, and both generate the same fault on the same problem.
Setup: ISE 6.1.03, EDK 6.1.02, ModelSim SE 5.8 and 5.7, with/without CoreConnect installed EDK Simulation Settings: HDL=VHDL EDK Library=C:\EDK\mti_se\edklib Xilinx Library=C:\EDK\mti_se Simulation Model: (Same error with both Behavioral and Structural) (all libs compiled without problems, modelsim.ini correctly setup)
Both behavioral and structural generate the following error during loading, after a bunch of models are compiled into modelsim. ( after executing do ../../data/testbench.do):
(Without CoreConnect installed) # Loading work.testbench # Loading work.uart_rcvr # Loading work.mt46v32m8 # Loading work.pci_targ32 # Loading work.AT24CXXX # Loading work.plb_monitor3x # ** Warning: (vsim-3009) [TSCALE] - Module 'plb_monitor3x' does not have a `timescale directive in effect, but previous modules do. # Region: /testbench/plb_monitor # Loading work.opb_monitor # ** Warning: (vsim-3009) [TSCALE] - Module 'opb_monitor' does not have a `timescale directive in effect, but previous modules do. # Region: /testbench/opb_mon # Loading work.dcr_monitor # ** Warning: (vsim-3009) [TSCALE] - Module 'dcr_monitor' does not have a `timescale directive in effect, but previous modules do. # Region: /testbench/dcr_monitor1 # ** Error: (vsim-3170) Could not find 'work.glbl'. # Error loading design # Error: Error loading design # Pausing macro execution # MACRO ./../../data/testbench.do PAUSED at line 92
(With CoreConnect installed) # Loading work.testbench # Loading work.uart_rcvr # Loading work.mt46v32m8 # Loading work.pci_targ32 # Loading work.AT24CXXX # Loading work.plb_monitor3x # Loading work.plb_monitor_comp3x # Loading work.opb_monitor # Loading work.opb_monitor_comp # Loading work.dcr_monitor # Loading work.dcr_monitor_comp # ** Error: (vsim-3170) Could not find 'work.glbl'. # Error loading design # Error: Error loading design # Pausing macro execution # MACRO ./../../data/testbench.do PAUSED at line 92
Again, this error occurs using modelsim 5.8, 5.7, ML300 EDK Ref design
1 or 2, with or without CoreConnect, and under Behavioral or Structural simulation.Is there any way to get this to work? I have been over this many times, but always with the same results.
On another note, when structural model is used, clocks_0_wrapper.vhd in projects\ml300_edk2\simulation\structural complains about three cases that are type integer but should be type real (the two cases where the period is set to 10 instead of 10.0, and the one case where the 30 should be 30.0).
# -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package vital_timing # -- Loading package vcomponents # -- Compiling entity clocks_0_wrapper # -- Compiling architecture structure of clocks_0_wrapper # -- Loading entity bufg # -- Loading entity fdp # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package vital_primitives # -- Loading package vpkg # -- Loading entity srl16 # -- Loading entity ibufg # -- Loading entity vcc # -- Loading entity gnd # -- Loading entity lut1 # -- Loading entity lut2_l # -- Loading entity lut3 # ** Error: clocks_0_wrapper.vhd(223): Type conflict in integer literal. Type real versus integer. # -- Loading entity dcm # ** Error: clocks_0_wrapper.vhd(258): Type conflict in integer literal. Type real versus integer. # ** Error: clocks_0_wrapper.vhd(292): Type conflict in integer literal. Type real versus integer. # ** Error: clocks_0_wrapper.vhd(347): VHDL Compiler exiting # ERROR: C:/Modeltech/win32/vcom failed. # Error in macro ./system.do line 9 # C:/Modeltech/win32/vcom failed. # while executing # "vcom -93 -work work clocks_0_wrapper.vhd # "
(the fix for these three errors is to append a "'.0" to each integer, happens on structural and not behavioral simulations). Both the old ML300 EDK Ref #1, and the new Reference packet complain about integer->real problems on this clocks_0_wrapper.
Thanks, Tony