I want to use the FSL bus to connect two microblazes together. Because I am not familiar with the FSL bus, I first added a peripheral core using the configure coprocessor wizzard, to instantiate a default paripheral, together with the FSL drivers. However, when I run the SW application it stalls when writing to the FSL bus. I don't get any response afterwards.
First, I did not made any changes to the instantiation of the fsl bus. Later on, I changed the clock connections (later on, also in the fsl's mpd file). Unfortunately, none o these measurements made any difference.
Is there anyone that can provide me an example design that successfully uses the FSL bus, together with the application software (or a stripped version)? I can not find any satisfying reference designs on the web, nor on the Xilinx site.
familiar with the FSL bus, I first added a peripheral core using the configure coprocessor wizzard, to instantiate a default paripheral, together with the FSL drivers. However, when I run the SW application it stalls when writing to the FSL bus. I don't get any response afterwards.
on, I changed the clock connections (later on, also in the fsl's mpd file). Unfortunately, none o these measurements made any difference.
the FSL bus, together with the application software (or a stripped version)? I can not find any satisfying reference designs on the web, nor on the Xilinx site.
You must instantiate two fsl bus, to connect two uBlaze, one for each sense of communication. In each instance, you should connect FSL_Clk,Sys_Rst, FSL_M_CLK and FSL_S_Clk (all three clocks together). Bot uBlazes should work at same clock frequency
You should also use the non-blocking versions of read/write functions (nput, ncput, nget y ncget).
not familiar with the FSL bus, I first added a peripheral core using the configure coprocessor wizzard, to instantiate a default paripheral, together with the FSL drivers. However, when I run the SW application it stalls when writing to the FSL bus. I don't get any response afterwards.
on, I changed the clock connections (later on, also in the fsl's mpd file). Unfortunately, none o these measurements made any difference.
the FSL bus, together with the application software (or a stripped version)? I can not find any satisfying reference designs on the web, nor on the Xilinx site.
I'll try to explain me...in English o.O :-/ FSL bus works in one direction: if you connect the peripheral or ublaze to FSL master, you can write. If you connect the peripheral or ublaze to FSL slave you can read, then if you want to write and read with the same ublaze or peripheral, you need 2 FSLs.
I had problems with my FSLperipheralublaze and with ublazeublaze connection by FSL. The reason was the signal "External Reset Active High", by defect, it was 1.
If you add the 2nd ublaze, also you must add the bram block, lmb bus...and you must verify that the bus interface is correct, that all the necessary ports are connected (for example, when I added the 2nd ublaze, EDK 8.1 don't add "sys_clk" to my ublaze and I had to put it in "system.mhs") and that bram block, lmb have addresses.
You don't need to connect the three clocks, if you have synchronous transmission, only the FSL_Clk is necessary. To write with ublaze you should use the function: "putfsl(data, 0)" ('0' is the fsl id) and to read: "getfsl(data,0)". In the case of FSL peripheral, you should use the signals FSL_S_EXISTS, FSL_S_DATA, FSL_M_WRITE....see the FSL_v20.pdf.
It did help me a little further. I am able to generate a system.bit and download.bit file now. However, I get no response from any of the µblazes. One is connected to the uart and external memory, the other only has access to its local bram memory. Is it required to write separate linker script files for each microblaze?
Regards,
Gerd
PS: thank you marada for your time, you helped me a lot!
It is necessary to write one linker script for each ublaze (one "*.elf" for each ublaze). When you add software application project, you have to specify the ublaze in that software works.
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