Hi There.
Xilinx CPLD XCR3384XL with speed grade -7 have (according to the datasheet) a maximum clock frequency at 135MHz. How have they found that number?
I have some timing problems on a FPGA and that trigged my curiousity. (I am assuming that they use a likewise method to find the maximum clock frequency in CPLDs and FPGAs, (but I'm not sure)).
Raymond
That only allies to trivial functionality. Note that as soon as you ahve some synchroneous counters or so, this maximum frequency comes down considerably.
Rene
-- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.net
In CPLDs the most usual way to calculate this was taking the output of a flip-flop in one macrocell to the input of a flip-flop in another macrocell running in a simple non-extended p-term mode. Some vendors will give a frequency between macrocells in the same block but more often than not the system figure is between 2 macrocells in effectively different blocks (worst case no extra p-terms). Some of the newer CPLD technologies may blurr this defination if I have not already lost you this defination.
FPGAs are not so simple. Some years ago Xilinx talked about a 1GHz counter running but certainly wasn't system frequency. The different vendors do put different biases on their numbers so my personal defination for SRAM type architectures is the speed for an average design with about 3 levels of lut logic average. Very roughly Spartan-3 gets about 150Mhz on my metric a Spartan-2 goes above 100MHz etc. The thing is with FPGAs a lot of factors can vary the frequency reached not least the luck, or maybe it's skill, of the designer.
John Adair Enterpoint Ltd. - Home of UAP. Cheaper Boards for Students and Universities.
This the maximal frequency of a shift-register !
Regards, Laurent
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