Hi,
I am trying to implement a debug template in an EC-FPGA (LFEC20E) with the Lattice ispTRACY IP Manager.
I am facing some problems. Maybe someone of you has experienced the same and can lead me into the right direction.
Here are the steps I perform:
- In the ispLEVER Project Navigator I open under TOOLS the ispTRACY IP Manager
- In the ispTRACY IP Manager I define the RAM depth etc. under CUSTOMIZE, then I click GENERATE to generate the file.
- In the CORE LINKER I can connect the signals I want to look at with the generated I/Os of the generated template. When clicking OK a new top level file is generated ("eval_ddr_top_test_debug.vhd")
When importing this new top level file in the Project Navigator I see that in the new top level file there is instantiated a component "test_debug.vhd". But this file is missing. Instead there is just a file "test_debug_tmpl.vhd" which can only be imported as a package. So the component is missing.
Can someone tell me what went wrong or where to find the missing file?
Rgds Andrés