Symon,
I agree that a slit in the ground plane is going to be an impedance discontinuity for signals that cross the split.
For that reason, I would probably have any signals that cross the split have a continuous ground underneath them. That little bit of ground that now connects the "isolated" ground plane to the rest of the ground plane is also a DC short across the NEC-Tokin device, but from an AC traveling wave point of view, it is an open, as the power and ground currents return to the power supply, and are unlikely to return over a small bridge between two planes.
I admit that designing this way requires thinking of the DC conditions, then the AC conditions, on both the power, and the IO. It means you have all kinds of opportunities to make mistakes, and have worse behavior, too. Far simpler to stay with one good ground, and isolate only the power planes (or better yet, don't even isolate the power planes). But, does "simple" work?
Using the two port by just shorting the two ports together, and putting it on the far side of the pcb right under the FPGA also is a use model that might make sense. The issue there is how to connect it to the power and ground planes with as low an inductance (impedance) as possible.
I could not see the internal layers of the PS3 pcb, but I suspect they spent a lot of time thinking about this. For them, not only is their performance to worry about, but also EMI/RFI requirements for the many regions they wish to sell into (FCC Part 15, etc.).
Most engineers would rather just forget the power until the very end of their design and layout, and never have to really analyze the power distribution system (PDS). The PSD for the user's guide for V5 takes a "here is the BOM" approach: just use these caps, place them like this, and you are done. The solution offered may be overkill for some designs, but will generally be adequate for 99% of the applications. Those that take PSD design much more seriously, will do their own engineering, and provide their own solution.
Austin