Hi, there
I am designing an FPGA to DRAM interface, which uses 160MHz clock. The clock cycle is 6ns, after gate level simulation with DRAM model and FPGA netlist of my design, I realized that the propagation delay of IO pad and RAM summed up to higher than 6 ns,
As a result, during reading with t_CAS set to 2, I only see data stable on the 3rd clock edge instead of 2nd. From simulation it seems to me I shall play trick by sampling data on the 3rd clock, but I don't want to go unconventional.
Is that the correct way of doing things in the FPGA-DRAM design? What are the pitfalls?
Thanks in advance.