I'm uning an FPGA with a IP processor and it has an interface to INTEL and AMD FLASH devices. Both these devices offer burst operations for read. Namely the first read is at max access times (110 ns) but reads to the next few (3 or 15) address are much faster (25 nsec) in acesss times.
My question, has anyone developed logic to take advantage of this burst transfer? Or can anyone offer suggestions as to how to inplement this design?
There are a few more details in the rules for burst transfers but they are specific to each device.
I assume you mean something like Intel Strataflash which offers a page read mode using the ADV line?
It's pretty simple to implement. See how it's done with a processor (try the Intel PXA270) - get the development manual and look at the timing.
The basic trick in the state machine is to hold off after starting the burst read for some number of clock cycles, then treating all reads the same, so something like
// state BURSTSTART always @(posedge clk) begin holdoffcount
Let's see if I get it. Delay first access till required_wait_time is met. Then read as fast as possible untill burst length is completed. Repeat till done.
I need to look at last address accessed and apply rules for burst transferrs.
Looking in my PXA datasheet (I have a board with one, plus flash, SDRAM and all that junk), we find (a couple of the parameters) - I strongly suggest reading the developer manual so you get an idea:
MSC0/1
RDN. ROM Delay Next Access: Address to data valid for subsequent access to burst ROM or Flash is equal to (RDNx + 1) memclks. nWE assertion for write accesses to SRAM is equal to (RDFx + 1) memclks. The nOE (nPWE) deassert time between each beat of read/write for Variable Latency I/O is equal to (RDNx + 2) memclks. For variable latency I/O, this number must be greater than or equal to 2.
RDF: ROM delay first access. RDF programmed RDF value interpreted
0-11 0-11
12 13
13 15
14 18
15 23 Address to data valid for the first read access from all devices except VLIO is equal to (RDFx + 2) memclks. Address to data valid for subsequent read accesses to non-burst devices is equal to (RDFx + 1) memclks. nWE assertion for write accesses (which are non-burst) to all Flash is equal to (RDFx + 1) memclks. nOE (nPWE) assert time for each beat of read (write) is equal to (RDFx
1) memclks for Variable Latency I/O (nCS[5:0]). For Variable Latency I/O, RDFx must be greater than or equal to 3.
So there are different parameters for the timing for First access and subsequent access - that's what I was doing above.
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