when I want to use a SRL16, I have to "include" the component in my entity like this:
component SRL16 port ( Q : out std_logic; -- SRL data output A0: in std_logic; -- Select[0] input A1 : in std_logic; -- Select[1] input A2 : in std_logic; -- Select[2] input A3 : in std_logic; -- Select[3] input CLK : in std_logic; -- Clock input D : in std_logic -- SRL data input ); end component;
Can I find templates for these component declarations somewhere? In the lib.pdf I can find only instantiation templates. Besides that, I can not use the generic map (INIT => X"0000")... How do I do it properly? Are there any include files for all the design elements?
You can simply include the UNISIM library which contains the component declarations and attributes (black box attributes) for all of our supported components. I have included a simple example below that shows the instantiation of two SRLC16E's and a MUXF5 to produce a dynamic addressed,
32-tap shift register. Also notice that I have included the generic map for INIT in my instantiation. This will be forwarded onto the PAR tools to initialize your SRLC16E primitives. This code was compiled by XST so I am unsure how other tools support passing the INIT attribute. Also note that for SRL16E's, you can generally infer them in your HDL much easier than instancing them.
Cheers... Mark Xilinx FAE
------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM; use UNISIM.VComponents.all;
entity srl16e_instance is PORT ( clk : in std_logic; ce : in std_logic; din : in std_logic; addr : in std_logic_vector(4 downto 0); dout : out std_logic ); end srl16e_instance;
architecture Behavioral of srl16e_instance is
signal srla : std_logic; -- output from U_SRL_LOW signal srlb : std_logic; -- output from U_SRL_HIGH signal srl_cascade : std_logic; -- cascade between LOW and HIGH
Libraries Guide is always a good place to start for component instantiation. There are some component templates also available in ISE under the little light style button.
If you want a simple shift then doing it in VHDL or Verilog is also easy. If write your code as the following style (VHDL shown), i.e. without a reset, most synthesisers will turn it into SRL16 based logic.
process(clk) begin if clk'event and clk='1' then
shift1 when I want to use a SRL16, I have to "include" the component in my entity
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