2) I am trying to figure out the best way to characterize some data coming into the FPGA. I have 4 pairs of LVDS data coming in to input pins. Eventually these pairs (which are from a 1-to-10 LVDS distribution chip - so they are copies of the same data) will be delayed, using the IDELAY, 45 degrees relative to eachother. I will have a 0 phase, 45 phase, 90 phase, and 135 phase data input. Using the DDR ISERDES at 1:8 deserialization, I will have 8 phases of data. The reason I am doing this is to recover the data. I know it is at 312 MHz, but I don't have a clock reference so I sample 8 phases of the same data and choose which one is the best (how is not important for this discussion).
I know that before I can delay the data pairs I must first '0 them out'. Due to board layout, clock skew to the ISERDES, etc, the data pairs (when ALL set to IDELAY = 0) will not be perfectly aligned. Currently, I am using the 312 MHz clock that I clock the ISERDES with to drive, via the ODDR method, an external data generator that sends one byte of data. I'm doing this so that I have a known data-to-clock relationship. I have the byte outputs of the ISERDES connected to ChipScope. I monitor the individual channels and one-at-a-time increment the IDELAY until the data corrupts. I know that the data is now being sampled right at the clock edge -- or at least close enough to break setup. I do this for each channel and I end up with 4 different IDELAY values. I then normalize these delays to the smallest one and I have the offset for each data pair. These offsets should align the data (within error and tolerance) to each other. I can then add the phase delays to the data pairs.
This worked fine when I was using the ISE and could use the ChipScope core inserter. Now I've moved to the EDK and have to use the ChipScope IP. I don't know if that has anything to do with anything though! My problem is that I can find the offsets to make the data align relative to each other, but the phases DO NOT work all the time. For example I can see that 4 phases 'see' the data, one doesn't and then the next one does. If everything is aligned correctly, I should not get any skips in detected phase. They should all be consecutive. Even worse, sometimes all 8 phases 'see' the data. This case is no good since there is no way to determine which one saw it first and therfore which one to use to forward data. There should be at LEAST one phase that does NOT detect the data!! Sometimes only one phase 'sees' the data. This should never happen either. The data is VERY clean coming from the test equipment and the distribution chip. I would say the eye opening is about 90% or more.
Can anyone see any major flaws with what I am doing? Is there a better way to guarentee these phase offsets? There is no way to get absolutely precise timing since the 45 degree increments of phase are not divisible by the IDELAY tap resolution. So I automatically have some error, but even with this error, this little scheme should work. Hell, I've seen it work consistently!! Hopefully I didn't just get lucky.
Sorry for the long post!!!