Hi, all,
sorry if the question appears stupid, I just want to get it start. also sorry about my poor english(it isn't my first language), hope you can understand what I mean.
My orignal design is done in VHDL. I have generate the edif from Xilinx. After reading most of the introduction, I think JHDL will be able to help me reading the EDIF file. What I try to do is read the EDIF file and conver it into my own structure (a chromosome of the circuit), follow by genetic algorithm, to produce a new function with the circuit.
In my understanding, edif file captures the gates, FF, and wires only, there is not architecture dependent. Let me know if I am wrong. Therefore, my questions are following:
- Why do we need to specify the architecture(target) during VHDL ->
JHDL using EDIFParser?
- Because JHDL doesn't support asynchoronous loop. Is there any software might do a better job than JHDL on simulating EDIF file as a black box with VHDL? It will be even better if it can be done by scrpit or command line (so that could be control by my java GA program)
Any help on this would be greatly appreciated. Thanks very much in advance.
YiQi Huang