# Divided by 11 in VHDL

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Hi, all
Synthesizer (XST) supports the divisor to be integer power of 2. Then
how about implementing an operation with the divisor to be 11.
result <= data / 11;
thanks.
Jimmy

Re: Divided by 11 in VHDL

Division by a constant isn't too hard--just multiply by its
eciprocal.  -Kevin

Re: Divided by 11 in VHDL

And constant multiplication can be small and fast
1/11 in binary is:
0.00010111010001011101000.....

a = (data >> 4) + (data >> 5) - (data >> 9) + (data >> 10)
get you 13 digits (usding three adders)

b = a + (a >> 10)
gets you 23 digits (using four adders)

c = b + (b >> 20)
gets you 43 digits  (using five adders)

and so on....

Kolja Sulimma

Re: Divided by 11 in VHDL

Please view the following with a fixed-space font:

If multiplying by the reciprocal isn't what you want, you can perform long
division where each new "digit" is another binary number.

For instance, 58/11
____101
1011)111010
-1011
-------
0111
- 0000
-------
1110
- 1011
-------
11

The result is 5 with a remainder of 3.

You can carry the result further to give a fixed decimal representation.

A better way to implement division involves an add or subtract at each stage
rather than a compare with subtract or do-nothing.  If an intermediate value
is positive, subtract and declare a 1 for that stage.  If negative, add and
declare a 0.  The result is a series of selectable add/subtract stages with
the sign bit of the previous stage selecting the add/subt.

_____101
1011)+111010
- 1011
--------
0111  (positive)
-  1011
--------
11000 (negative)
+   1011
--------
011 (positive)

The result is again 5 with a remainder of 3.  Be warned that negative
remainders will show up in the last stage when the last regular bit is 0.
The positive remainder is the last positive value encountered in the chain.
Or just add the divisor to the negative result for that same positive
remainder.

This is division.  It takes time to propagate through many carry chains.

Re: Divided by 11 in VHDL
If your dividend is small enough and your target FPGA has enough spare
memory, you also might consider table lookup.  Another alternative is to let
your synthesis tool create the table out of logic - write a program to
create the verilog or vhdl ( for (i=0; i<2047; i++)  print i, ":", i/11 );
etc).  -Stan