Hi everyone,
I've recently had to argue why it is not 'sane' to budget 500 hours of development against 200 of verification.
If you ask the FPGA developer he'd say a factor of 2/3 has to be considered for verification w.r.t. design (that I tend to agree to).
I'd like to give some grounds to those estimates and I asked the fpga group leader to compare among several completed projects what is this ratio. We are usually collecting lots of data on the amount and type of work we do every day and this data can be used to verify the verification effort w.r.t. the design effort.
His counter argument is that it is difficult to compare projects due to their peculiarity, implying that there's very little that we can learn from the past (that I obviously do not buy!).
As of your knowledge is there any source of - trusted - data that I can point at? Is there really a ratio that can be 'generally' applied?
Any comment/opinion/pointer is appreciated.
Al
p.s.: this thread is intentially crossposted to comp.lang.vhdl and comp.arch.fpga. Please use the followup-to field in order to avoid breaking the thread.