Dear all,
I have a microcontroller with an FPU which is delivered as an IP (I mean the FPU). In order to run at a decent frequency, some of the operations are allowed to complete in within a certain amount of cycles, but the main problem is that we do not know how many.
That said, if we run the synthesis tool without timing constraints on those paths, we have a design that is much slower than can be. Multicycle constraints are out of question because they are hard to verify and maintain, so we decided to set false paths and perform post-layout sims to extract those values to be used in the RTL in a second iteration.
There are several reasons why I do not particularly like this approach:
- it relies on post-layout sims which are resource consuming
- if we change technology we will likely need to do the whole process again
- we are obliged to perform incremental place&route since an optimized implementation (maybe done automatically) may have an impact on our delays.
So far we have not come out with an alternative solution that is not going to imply redesign (like pipelining, c-slowing, retiming, ...).
Any ideas/suggestions?
Al