[cross-post]path verification

Dear all,

I have a microcontroller with an FPU which is delivered as an IP (I mean the FPU). In order to run at a decent frequency, some of the operations are allowed to complete in within a certain amount of cycles, but the main problem is that we do not know how many.

That said, if we run the synthesis tool without timing constraints on those paths, we have a design that is much slower than can be. Multicycle constraints are out of question because they are hard to verify and maintain, so we decided to set false paths and perform post-layout sims to extract those values to be used in the RTL in a second iteration.

There are several reasons why I do not particularly like this approach:

  1. it relies on post-layout sims which are resource consuming
  2. if we change technology we will likely need to do the whole process again
  3. we are obliged to perform incremental place&route since an optimized implementation (maybe done automatically) may have an impact on our delays.

So far we have not come out with an alternative solution that is not going to imply redesign (like pipelining, c-slowing, retiming, ...).

Any ideas/suggestions?

Al

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alb
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So you paid someone for this?

I am not sure what you mean by "a certain number of clock cycles" and "do not know how many".

If it is all combinatorial, it will complete with some delay, not in some number of clock cycles. That is, the delay will not depend on any clock you supply. You then have to either be able to run the design through timing analysis and see how long that is, or the ones you bought it from should tell you.

Though more usual, the logic should have a signal indicating when the result is valid.

You could run the FPU in the timing tools with a variety (random) inputs and find out how long it takes. Then find the distribution of delays, and find a reasonable maximum. It might be data dependent and have a long tail. (A post-normalize shifter might depend on the number of digits being shifted, and the rare long shifts would have to be accounted for.)

The FPUs that I know of should be pipelined. (Is there a clock input?) You shouldn't have to do the pipelining, but you do need to know the number of clock cycles (and clock rate) for each operation.

If the design is encrypted, such that you can't look at it, they need to give you enough information to be able to use it.

-- glen

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glen herrmannsfeldt

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