I was wondering as to are there any good resources online /and or some tools to learn about formal design verification of large complex designs like for instance a processor.
Also a good paper reading list in the same field would be great as there are a tons of papers in this field on the ACM portal and I have no clue where to start from.
Thanks
--------------------------------- Kartik Krishnan kkrishnan[at]wisc.edu
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Formal Verification is usually divided in two subtopics:
- structural equivalence checking
- model/property checking
Structural equivalence is easy done, but gives you no idea wheter you hit your specification. However it's very important to ensure your netlist is still in spec, if your rtl code was in spec. Especially after doing "handinsertions" or using selfmade tools on the netlist.
Comercial tools for structural equivalence are
- LEC from Verplex
- Echeck from Prover
- Formality from Synopsy
- FormalPro from Mentor
Model checking techniques are very difficult for complex processors but would give you a safety you hit your spec (or miss zhe spec *g*). There are also commercial tools available, AFAIK is none of the tools able do do complex designs nowadays.
bye Thomas
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