I am trying to use Xilinx chipscope, but it is not working properly (probably mishandling by the user...). Perhaps somebody can give me some light...
I used core inserter, and I have a ICON and a ILA core. I want to monitor a SPI bus in a 2VP2 device, that has 12 RAM blocks available. I defined a 1 trigger port with width 1, set with the sclk (that should be around 10MHz). And I have a 40 data width bus where I try to see many data signals.
I can go to the point where I generate the programming file (bit file). Startup clock is set to JTAGclk, keep hierarchy is set to YES. I also generate (just in case) the mcs file and load my 18V04 EEPROM. I recicle power and then I click in the Analyze Design Using Chipscope. After opening the JTAG Chain (XILINX Parallel IV cable), it says that it found 1 core unit in the JTAG device Chain. But if I press the "trigger now" button, it does not give me the status of the lines. It enters a mode where it says"siting for core to be armed." and stays there forever. Am I setting the trigger in a wrong way?
We are talking about versions 7.1 os ISE and chipscope pro.
I would appreciate any input!