I'm attempting to use the CoreConnect BFM with a Verilog-based PLB peripheral (for a PowerPC-based design). I used the wizard to generate all of the VHDL parent and simulation files -- when I try to use the bfm_system project in XPS and run Modelsim, however, I run into a few issues. The first is that the unisims_ver library is not automatically being mapped at some point (even though it's in bfm_system.do: "vmap unisims_ver c:/xilinx/sim_iselib/unisims_ver/"), so it starts complaining about my instantiations of DCMs and various buffers (the primitives).
I got around that problem by changing scripts/run.do to read: vsim -L unisims_ver bfm_system
Now when I run it, Modelsim will compile the right Verilog files fine, but will stop with a strange error message. So far I've received:
- "Unresolved defparam somewhere" (an incredibly unhelpful error message)
- It will simply freeze at the end of loading the modules involved
Is the BFM toolkit not designed for mixed-language designs? What are my options for debugging DMA transaction errors?
Thanks, Kunal
(FYI -- EDK 8.2 + latest patches/updates, Modelsim 6.0 SE)