Antifuse, lower cost?

Where that matters, is in the impacts of < 100% yield. You can't really mount the devices before programing, and so suffer another handling step. Then you ideally need to be able to decide which devices are duds _before_ you mount them on your expensive PCB (that means costly vector testing), and finally, who pays for the dud's ? I think only TI still makes OTP CPLDs (Atmel have a couple of MilSpec ones alive )- everyone else has gone to EE, and that's on small/simple devices. Looking at Actel's latest push, I see their FLASH devices are pushed as low power (not their antifuse), and Actel claim the QuickLogic PolarPro benchmark as the worst battery life of the low power alternatives.

Pretty much places any OTP device in the NFND bucket ?

-jg

I think you missed Scott's point. He is saying that for a production of any volume, you can let the manufacturer program the devices. They are better equipped and at that point it adds little to the price. Let's face it, the cost of testing any large FPGA is not trivial and the cost of factory programming antifuse parts is lost in the noise. In fact, once you let the factory program the parts, you can likely save on test costs since you only need to test the logic you are using, just like EasyPath, if I have the right name. So factory programming will likely reduce the price of the antifuse parts over buying them yourself even without considering the cost of programming them in house.

If the programming were done with something other than electricity, the programming circuitry could be eliminated. I seem to recall a company that used to provide fast ASIC-like prototypes with laser cutting of traces. I have not heard much about them lately. What was the down side of this approach?

OK, but I don't see a lot of OTP vendor noise offering this. Plus, a key AntiFuse pitch is security, and that paranoid user base is not likely to ship code out the door...

Also, if you shove programming 'out', how exactly do you develop/change the design ? [maybe like another poster, who uses RAM fpgas to develop for OTP ones ? ]

-jg

I'm sure there are others, but I think you are referring to Altera's "Hard Copy", which is technically a "structured ASIC". It's essentially an ASIC comprised of a selection of pre-wired IP components from their FPGA lines. (You get the same PLL/DLL's, M4K blocks, etc as a real FPGA, but hard-wired together based on your netlist)

The advantage is that you get to develop your design in an FPGA, then port to an ASIC little or no modification to the original design. You get a high level of confidence that if the design worked in the FPGA, it will work in the ASIC, since the ASIC is essentially your FPGA design with "hard" routing. The ASIC will even replace the FPGA on your board without any modifications, since the pinout is identical save the configuration pins. Lastly, you get an automatic speed boost (in some cases, up to 100%).

The structured ASIC's do cost more than a true ASIC, so you have higher recurring costs, but the initial investment is lower (by an order of magnitude - $100k vs $1M), and you lose less of your NRE, since you aren't reworking the design to operate in an standard ASIC flow. There is also the lock-in problem as well. If the firm ever quit making the parts, you are SOL, as they own most of the ASIC IP. You have to hope that you pick the right structed ASIC firm, or do a lifetime buy at some point. The only saving grace is that you still have the original design files, and can begin migrating to another process while you sell off your current inventory.

I haven't had a chance to use the process myself, since my employer can afford to use FPGA's, or when the time arises, pony up for a true ASIC, but it makes sense for middle tier players. You get most of the advantages of an ASIC without the ridiculously expensive upfront costs.

And let me expand on that. The dirty secret of our industry is that reprogrammable FPGAs are being used to cover for lacks in testing and vector creation. I came from a full custom background, and its shocking what passes for simulation and test now.

The point is, when you reach production with these devices, the game changes. Our little lab rats are not sitting there plugging in the devices, so they are being programmed by the distributor, or in system. In other words, what was once formalized testing is now ad-hoc. Is this an advance?

I was very interested in the technology myself, until I ran into a veteran of the laser configurable chips. In a word, their contamination issues were paramount. Apparently blasting away at metal, or the need to have openings in the passivation, or both, was contaminating the chips.

In any case, this method started in the days of two level metals. I doubt its equally attractive against eight or more metals, when you can only gain access to perhaps the top two.

Scott Moore

I've looked at it, and all I can say is "grow a pair", and invest in COTS to get portable between fabs.

Scott Moore

PS. We are FPGA to proof full custom designs, so there is my bias right there.

Apologies, that would be Customer Owned Tooling, not that other acronym.