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Altera Avalon Address format between Master & SDRAM controller?

Hi there group,

I'm implementing a user defined Master interface to the Avalon Bus using Altera's Stratix FPGA and read through the documentation on the Avalon Bus requirements and the SDRAM controller as a slave, and I'm still not quite getting how the SDRAM controller interprets an address supplied by a Master peripheral? The SDRAM has a total of 22 bits (12 bits row, 8 bits column, & 2 bits bank). I am provisioning the address width on my master to be 32 bits wide of which the top 10 bits are stuffed with 0's and the remaining bits are column-row-bank respectively. Is this a correct understanding on how to provide the address to the slave peripheral sdram controller? If not, I'm definitely missing something here.

Also I suspect this provided address is also de-correlated from the address assigned in the SOPC builder configuration wizard? That if i have a Master peripheral talking to multiple slaves at different clock cycles within my state machine, how do I specify which slave peripheral I am targetting and guarantee that I'm talking to the right one?

Help would be appreciated Pino

Reply to
pinod01
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Pino,

It is much easier than you think. With Avalon, your master emits the address it wants, and that is all there is to it. SDRAM appears as an addressable range of memory (depending on the size of the SDRAM device you're interfacing to). There is no need to worry about column-row-bank business; the SDRAM controller handles that for you.

For your second question, again, you emit the address you want to along with a read or write signal and that's it; the generated Avalon bus logic then accesses the appropriate slave peripheral as defined in your address map.

Jesse Kempa Altera Corp. jkempa -at- altera -dot- com

Reply to
kempaj

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