74 logic to CPLD. how easy for a Newbie?

QII and the Altera MAX parts are a quick learn , if you are a 74 designer you should be implementing lots of stuff in a month. Various varieties of the MAX parts are 3V and 5V .. etc.

I may suggest that for $99 arrow sells an Altera MAX development board , includes QII and board with a max part with buttons and lights and osc, very easy to learn how to implement lots of neato logic things and then quickly try them on a real board.

Verilog is much easier to learn and use than VHDL, unless someone is forcing you to use VHDL choose Verilog. If you know any C you should be able to learn enough Verilog to do a simple 74xx conversion in a week. BTW how old is this design? except for some bus transceivers I haven't used any 74xx stuff for 20 years.

Your design is fairly simple and time is short, so consider using Quartus schematic capture for your first design.

File, New, Block Diagram, RightClick Insert, Symbol, libraries\other\maxplus2\74374 LeftClick.

... and you're off to the races.

Since you already know the circuit, you can likely get it functioning without simulation.

Learn the HDL for a testbench for your schematic block using the Modelsim CD. Then redo the design in HDL and rerun the testbench as a tutorial.

-- Mike Treseler

Assuming you're not learning logic from scratch: When I first started with CPLD's I was using a rather early Xilinx Foundation, covertly provided to me, and it went something like this: Day 0: Be friendly towards the FAE when he's on-site anyway. Get a hint. Day 1: Get the tool installed. Why the hell won't my schematic of a simple buffer translate? Day 2: Discovered that I needed I/O buffers. Place a single counter into the design, figure out how to put the pins where I want them. It translates and fits! Build a small board with an oscillator, an XC9536, and a LED. Borrow a Parallel-III cable. Day 3: Programming works, LED is blinking (very quickly). Conclude that this is feasible. Day 6: Call the friendly FAE. "This is a tool bug. Do this instead." Get a few tricks and nasty jokes. Day 10: Create a better Parallel-III cable, give back the original. Day 20: "Parallel port to IDE interface CPLD" is working. The prototype has analogue bugs and I'm out of room in the XC95108. Add an external filter as this is hobby and I'm living off a friendly Xilinx FAE and samples.

Day 200: Design-in lots of Xilinxes: I know they will work and the FAE is nice.

As to the Schematic|VHDL|Verilog debate|mudthrowing|discussion, I've used all three professionally. It's somewhat like the assember|Pascal|C programming-language question. It depends on what you're doing which one is best, but I believe that for the beginner who comes from a schematic world, a quick success experience is important. Once you reach the level of complexity where you're spending as much time figuring out your own schematics as designing, learning one of the HDL's is a good idea. They are extremely powerful tools once you master them.

An in-system programmable CPLD like the XC9572 is nice. It's also my preferred device for home projects, no reason to hide that. They are a bit power hungry, but they are well behaved, their routability is good enough that you generally don't have to think about it, and hard to kill. The 3.3V CoolRunner XPLA3 is nice too, but the tool is not as perfectly polished as for the old XC9500 series and the device is a bit tighter on resources. Those are Xilinxes, Xilinx' later tools are a bit weak on the schematic side, I prefer the older Foundation 3.3 for schematics but that's me. If you known an HDL the later tools work perfectly. Altera has some nice xPLDs too but I've only used their FPGA's so I can't comment on those other than that I know we use them in volume, and they work. Their latest Quartus tool works as well as Xilinx'. I've used Lattice's older devices, and back then they and the tool were the reason I ended up in the Xilinx/Altera camp.

Whatever you do, choose something in-system programmable. It's invaluable once you enter the bughunting phase.

When calculating the total cost, don't forget the programming connection and the time spent programming the device.

/Kasper

VHDL is by far the language to use for FPGAs. According to 2001 statistics 65% of the FPGA market uses VHDL and 15% uses Verilog.

What makes VHDL hard to learn is its use of strange logic operators (and, or, not, xor) rather than the cryptic (but perhaps familar ones of C). This is the main extent of the similarity of between Verilog and C.

Some consider VHDL hard to learn due to its strong typing. Strong typing requires you to learn some rules for correct expression formation. These rules are explained in the paper, VHDL Math Tricks of the Trade, which is available at:

So some consider Verilog easier because it does not force one to learn strong typing rules.

One company that delivers IP in both VHDL and Verilog, requires its Verilog designers to use a lint tool which enforces' VHDL strong typing rules on Verilog. In a paper they presented at DVCon last year, they stated that 75% of the time a strong typing rule violation was a real bug in the design. Just a little food for thought.

Verilog also requires you to learn adhoc rules about proper use of assignments so you can avoid execution race conditions. If you don't follow these rules, you code may execute differently on different simulators. There is nothing in the Verilog simulator that warns you of anything being wrong.

Have a bad day coding with Verilog, you better have a lint tool and a good testbench.

Have a bad day coding with VHDL and you will get abused by the compiler but you will not introduce bugs into your design.

Personally, I cannot see why anyone would use Verilog. I would not recommend it to anyone (other than the competition :)).

Cheers, Jim Lewis

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SynthWorks Design Inc.           http://www.SynthWorks.com
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B. Joshua Rosen wrote:

> On Tue, 21 Oct 2003 07:23:25 -0700, Carl wrote:
> 
> 
>>Hi,
>>
>>My apologies if this is not the most appropriate group for this query.
>>
>>I am starting to have great difficulty sourcing some 74 logic parts from
>>my design in SMD (at least in small volumes). As I now have the chance
>>to make a new PCB revision I am wondeing if I couldn't do away with the
>>logic all together and use a PLD (CPLD).
>>
>>So for those who know the learning curve well,
>>
>>I have never used PLD's before, but have used PIC's (asm) and was
>>wondering if it is realistic for me to grasp enough of PLD design (not
>>necessarily VHDL) to implement some simple logic functions within a
>>month or so?
>>
>>Or is this likely to take far longer?
>>
>>I was playing with the Altera Quartus II software and it seems that by
>>using existing blocks this could be fairly straight forward.
>>
>>What do you think and what would be a good entry level device?
>>
>>Any comments would be greatly appreciated.!
> 
> 
> Verilog is much easier to learn and use than VHDL, unless someone is
> forcing you to use VHDL choose Verilog. If you know any C you should be
> able to learn enough Verilog to do a simple 74xx conversion in a week.
> BTW how old is this design? except for some bus transceivers I haven't
> used any 74xx stuff for 20 years.

What all the other guys said, plus this:

Be *very* careful about gated clocks and async resets. It's common for an SSI or MSI TTL design to do all sorts of funny tricks with async resets or clock gating.

A direct translation of your TTL design to CPLD isn't guaranteed to work. Failures are usually due to glitches or races. Don't be discouraged though, as it should be easy to do some minor amount of redesign to avoid those problems.

Read up on synchronous design techniques.

Regards, Allan.

First you need to collect your logic, and tabulate the IP's, OP's, and buried nodes, required. Good devices could start at SPLD 16V8 (8i8o), 22V10 (12i10o), or 32 Macrocell CPLD (32io,2-4ip) on up.

Next look at the Power supply budget : Voltage and mA/uA, and if can you tolerate multiple Vccs.

For simple logic you do NOT have to use Verilog or VHDL. Most tool flows include simpler Boolean Eqn entry options in the form or ABEL or CUPL.

Here you enter eqns like

CS4 = !(A12 & A13 & A14 & !A15);

Qs1.d = Shift & Qs0 # Load & Ds0;

This is very similar to the Assembler you are used to. The tools can also run command-line, just like the ASM.

-jg

You can use Xilinx's XC9500 series for smaller designs, they hold the program in flash memory inside the chip, and are pretty cheap. For larger designs, there is the Spartan series, a bit more expensive, and it needs an external serial PROM and a reset circuit. These are both 5 V parts, although most of the new stuff from Xilinx is

3.3 V and less. They have a schematic entry package in their ISE software. Oh, yeah, all their software dropped support of all 5 V parts about 3 years ago. So, you have to get ISE 4.1 or 4.2 to get support for those 5 V parts. Their schematic entry package is not to my liking, after suffering with it for some time, I have figured out how to do schematics in Protel 99 and send VHDL over to the Xilinx tools. If you have a favorite schematic package and it can export VHDL, you can probably do the same.

Jon

You can use Xilinx's XC9500 series for smaller designs, they hold the program in flash memory inside the chip, and are pretty cheap. For larger designs, there is the Spartan series, a bit more expensive, and it needs an external serial PROM and a reset circuit. These are both 5 V parts, although most of the new stuff from Xilinx is

3.3 V and less. They have a schematic entry package in their ISE software. Oh, yeah, all their software dropped support of all 5 V parts about 3 years ago. So, you have to get ISE 4.1 or 4.2 to get support for those 5 V parts. Their schematic entry package is not to my liking, after suffering with it for some time, I have figured out how to do schematics in Protel 99 and send VHDL over to the Xilinx tools. If you have a favorite schematic package and it can export VHDL, you can probably do the same. The Xilinx libraries have most of the standard 7400 series parts as standard items. You can mix and match 74xx and basic gate and FF components from the library in your schematic. With a CPLD (XC9500 series) you can put dozens of 74xx parts into one $10 chip. With the FPGA (XCS - Spartan series) you can put several large boards worth of SSI-MSI chips onto one $15 - 30 chip. I have a product that has 4 24-bit pulse rate generators with controllable pulse width and setup and hold times, 4 24-bit quadrature encoder counters plus a bunch of digital I/O pins and an IEEE-1284 bus controller, all in one $30 Spartan XCS30 chip. There is a 74HC14 used mostly as a reset generator, and a 74HC4538 one shot used as a watchdog timer, otherwise, the Spartan has all the logic on the entire board.

Jon

Thank you everyone for your advice,

I think I have been inspired sufficiently to get a dev kit to play with. This is a very mature product that still works really well; judging from your responses however, I feel it would be an important step for me to be able to ditch thinking in 74 numbers and it's something I really should have done before (Plus a big wad a brownie points never hurts).

One more quick question though..

My design also has the following elements, which of these couldn't get squeezed into a CPLD?

4046 PLL's (Phase comparator 2) various Comparators

Thanks again everyone.

Carl.

In theory, you can do this in a CPLD. In practice, the performance may be poor with respect to the original.

Note that the 4046 PC2 isn't a particularly good phase comparator to start with (with respect to better designs such as the 74HC9046). The '9046 has a current source & sink output that cannot be done (directly) in a CPLD. The '4046 has a tristate output that's just like a regular tristate output on a CPLD.

Maybe, maybe not. Some CPLDs have schmitt trigger inputs. Some FPGAs have differential inputs (e.g. LVDS) that behave like a comparator. Don't expect any CPLD or FPGA to give you low noise, precision thresholds like a comparator though.

Regards, Allan.

I bought a Parallel-III cable years ago, never used it though, but am "close" to using it now. What were your problems with the cable?

Cheers

Klaus

The primary problem is not so much the cable, it's an odd (now rare/extinct) breed of parallel port:

On some parallel ports, when the driver writes to the port, instead of just changing, the signal lines will be undefined for around 100 ns. This results in extra clock pulses and wrong data being clocked into the device. The cause is the behaviour of the x86 ISA bus (on which the parallel port still resides, even in my K7 machine): The write strobe is asserted before data i stable; For this reason the original IBM design calls for an edge triggered latch but some used level gated ones. Certain Compaq, Olivetti, and Siemens Pentium-1 machines had the problem.

/Kasper

I suggest that you put that on the back burner to start with.

You will have to read the data sheets for the CPLDs you are interested in, probably many times. While you are doing that, keep an eye out for things that match the data sheets of the parts you are trying to replace.

Basically, CPLDs/PALs work great for traditional digital problems. That is: clumps of FFs (state machines, counters) have a max frequency FFs have setup/hold and clock to out gates/logic have prop times All that gets complicated by routing/placement. For the simple devices you can generally do it in your head.

If you want to do analog-ish things, you have to find a circuit that will work given the specs you can find in the data sheet. (Sometimes you have to use your imagination and/or read between the lines.) If you can find the specs you need, then you can build your circuit. But I doubt if you will find much that helps for PLLs or comparators.

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