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5V I/O with 1.8V Core

"Nicholas C. Weaver"

I believe foundries offer this already.

Maybe Austin L could confirm if Xilinx are using this ?

In noise immunity topics, we've seen the point made that the CONFIG cells have significantly different, and better, noise immunity ( so config corruption is less likely than logic corruption).

Why ? Sure, more steps will be needed - but spacing ?

There would be a case for really pushing the Speed rules for LOGIC, but going for MAX Yield (ie slightly relaxed geometries) on the CONFIG cells (lots more of them, _and_ they are not 'picosecond paranoid' ). There would be some trade off on CONFIG time, and leakage Current in a variable threshold design.

I think this could be checked experimentally - drop Vcc, and LoadCLK, and plot Config verify fail Vcc/Freq curve. Then create a LOGIC fabric shifter, and do the same for it.

-jg

Reply to
Jim Granville
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I'ts just an observation that anything special tends to require greater spacing as well as greater steps. I don't have/haven't seen any actual design rules with multiple Vt threshholds, but the most sophisticated I've delt with is .18 micron.

Additionally, for all but FPGA, mixing high Vt and low Vt transistors very close would not be a huge benefit compared with just having the two.

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Nicholas C. Weaver                                 nweaver@cs.berkeley.edu
Reply to
Nicholas C. Weaver

Jim,

Been there, done that.

Still doing that, and more. It is very favorable to do special things with the cmos configuration cells (we call them CCC's) rather than SRAM memory for configuration. Our CCC's are 20X or more robust than SRAM to SEUs, and all for good reasons.

Aust> "Nicholas C. Weaver"

Reply to
Austin Lesea

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