Hi
Im upgrading an old HW-design for a client, which includes and Xilinx XC9536XL. Unfortunately he only seems to have the .JED file, which gives me a hard time figuring out how the constuction was intended to work.
I wonder if there is a simple way to reconstruct the boolean equations from the JED file?
Kresten
"Kresten Nørgaard" wrote
me
from
For some PLDs there are JED2EQN pathways - ask Xilinx ?. Where this does not exist, you have some choices a) reverse engineer the JED - not impossible, but will require many iterations and a good understanding of the CPLD structure to get the info. Creating simple testcase templates with the tools helps identify the fuse pattern areas.
Likely to be more productive to 'have a really good look for the source' :)
b) Reverse engineer the function. They _should_ have a schematic, and info of things like memory or IO mappings. You can also generate JED test vectors, and use these to exercise the existing device, and confirm the new one is functionally identical.
Be aware that because of the internal AND.OR structure, you can create two JEDs functionally identical, but that fail a compare.
-jg
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