1GHz FPGA counters

(snip)

If I understand the way it is done in some experiments requiring sub nanosecond timing, they call it a TDC, time to digital converter, and it seems to work by generating a ramp signal, and digitizing it with a flash A/D converter at the trigger point. Maybe a 100MHz counter, and the sawtooth/ADC to get the low order bits. It might take some calibration, but numbers in the 100ps range seem to be easily obtained. 100MHz and a 6 bit ADC would give

10ns/64 or 156.25ps.

-- glen

In some TDCs, the ramp is generated by trigger signal and sampled by the steady clock. If the ramp came from the clock, you'd have large uncertainties near the corners; the harmonics to get a "nice" corner are also huge and outside the range of affordable A/D converters. By designing to guarantee a (reasonably) linear ramp, the trigger-signal's start ramp can be sampled in 2 spots on the ramp far from the "corner" giving the precise delta voltage for one sampling clock period. The stop ramp can also be sampled in 2 spots on the ramp and should have the same delta voltage. The voltage difference between these two ramp sample pairs relative to the voltage difference for one clock cycle will give you the offset in time relative to one clock cycle. But I hate precision analog beyond a few 10s of MHz.

I prefer sinusoids. Generating a reference sine and cosine pair at a high frequency (say 200 MHz so nice A/Ds can be used), the two sinusoids can be sampled with a dual-channel A/D using the incoming signal as the trigger to get a sine/cos voltage pair. As long as the maximum amplitudes are measured or otherwise calibrated and the phase offset is close enough to 90 degrees (which can be calibrated downstream), the phase of the incoming signal comes straight from the arctan( sin/cos ) without ambiguity since the signs of the sine and cosine dictate the quadrant. The components to produce the clean sin/cos pair are widely available since many RF systems use I/Q modulation/demodulation or other "quadrature" techniques. With 10 bit A/D converters, the phase resolution is about 11 bits or about 2.5 ps resolution at 200 MHz; at this point the reference jitter and A/D aperture uncertainty will be major factors in the error budget. The incoming signal can transition as fast as the A/Ds can sample.

It's a pretty system and FPGAs can do a great job with cartesian to polar conversion.

(snip of TDC description)

That sounds like a better description of the one I was trying to describe. It is sometimes used for high resolution timing of photomultiplier tube pulses. You could use the semi-analog method to measure the time relative to a steady clock, and count the number of clock cycles in between.

The main point I was trying to make was that there are some partly analog methods that can get timing resolution finer than affordable digital methods. There are some that claim 50ps.

(snip of sin/cos TDC description)

-- glen

: (snip of TDC description)

:> In some TDCs, the ramp is generated by trigger signal and sampled by the ...

For TDCs, look at

-- Uwe Bonnes snipped-for-privacy@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt

--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

I've been thinking about this again, because the OP's question was physics related, so from their PoV: does using mixed settings in the posedge/negedge option of the FFs introduce a systematic error because the inverter on half of the FFs causes additional delay? Or is there no additional delay (because of how the FFs are built in silicon or some other reason)?

regards,

-g

If you simply invert, then you have both the delay miss-match issue, and also any duty cycle variation from 50.00% becomes a time skew. If you use 4 possible phases from the DCM, presumably that removes the duty cycle issue, but you will still have LSB step errors in precise timing. My understanding of the DCM is these are

how closely matched are the IOs assuming you stay within the same bank?

1ns is only about 140mm of trace on FR4

-Lasse

140 mm is a long distance, almost six inches in Imperial units :-) With careful lay-out you can avoid errors down to From: Lasse Langwadt Christensen

it's about the same as the distance around a FF1152 package ;)

-Lasse

Correct, jogging all the way in a circle around that package is >130 mm. Jogging in wide circles may be a healthy exercise for humans, but it is not recommended for timing-critical signals. Peter Alfke

I think it's reasonably common to use a "long" trace on a PCB as a short delay. But suppose the delay is "timing-critical"?

How stable is FR4 over temperature? Humidity? Is there anything else that influences the delay on an existing board?

How repeatable is the delay from batch to batch? I think the delay only depends upon the dielectric constant and that probably depends upon the ratio of glass to plastic. Are there layout patterns that make it easier for the board house to make the same result consistently?

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Hal,

The use of pcb traces for circuits (delays, filters, etc.) has a long tradition. I have heard that the characteristics can be held to +/- 3% easily (almost without thinking as long as the materials used to make the board are specified: layer thicknesses, pre-preg thicknesses, copper thickness).

Cell phones are just one miracle that use a lot of pcb 'components'.

Aust>>Correct, jogging all the way in a circle around that package is >130 mm.

I looked for some TDC descriptions before posting, but I didn't find a good one. Within the above site,

seems to be the one with an actual description. This is a little different from the one I knew about before, but interesting anyway. They call it fully digital, though it depends on the delay through a series of inverters.

-- glen

Hi,

I am currently developping the oposite and came up that it might not be good to use an FPGA because of routing delays that might no be equal on all paths. My suggestion is to use a cypress Roboclock to get four phases and use a CPLD to modulate the pulse. The CPLD path delays are expected to be allmost the same as long as you take care not to use more than five PTs.

So in my application I have a 100MHz clock with four phases (1.25ns increment) and the FF triggering at rising and falling edges giving 800MHz resolution.

My interrest is to know whether I can archive the same precission (

Hi,

I am currently developping the oposite and came up that it might not be good to use an FPGA because of routing delays that might no be equal on all paths. My suggestion is to use a cypress Roboclock to get four phases and use a CPLD to modulate the pulse. The CPLD path delays are expected to be allmost the same as long as you take care not to use more than five PTs.

So in my application I have a 100MHz clock with four phases (1.25ns increment) and the FF triggering at rising and falling edges giving 800MHz resolution.

My interrest is to know whether I can archive the same precission (

(snip)

I just learned about the roboclock last week. According to the sheet I have it only goes to 80MHz. Maybe there are newer ones that go faster.

"almost the same" depends on what precision matters....

It is not clear what you are trying to do. From the application, more than your questions, it sounds like you wish to control an edge position to a precision of ~100ps ? On what lower Frequency ?

You can use multiple phase clocks to improve timing precision above

1/fclk and getting to 1ns has the consensus of do-able.

If your modulator frequency is high, you can also use rate-multiplier edge modulation, to give better audio-band precision ?

To get to 100ps is going to push away from the realm of clock edges, and into the realm of silicon delay lines.

I think there are test modes in the DLLs, and carry chains are the user fabric with the most speed.

Philip F. made this comment in another thread re Virtex4 > Looks like a 32 bit counter hits 360 MHz, in a -11, with preliminary > speed files. Gotta love the 41.5 ps/bit carry chain.

that suggests a time granularity of sub 50ps will be doable in the next generation devices - these delays need continuous calibration, as they will be Vcc/Temp/Process dependant.

-jg

I expect this within 100ps when propperly floor planed.

Ok, wasn't quite clear. I want to controll the edge with a selected phase with 1.25ns increment. The error between the different phases should not be more than 100ps. So I have an effective sampling rate of

800MHz and an error of 100ps max.

That's what it is.

I do not think that I can get the same precision. As long as the error is predictable I can correct it (noise shaping).

The 100ps are not the resolution. It's the phase error.

It's interresting. But can I keep the different on chip routing delays of the different phases within 100ps to each other? The DLL surely will give me the resolution. But if one delay is some

100ps longer than the other there will be the same difference as phase error on the output for some patterns

The simpliest way is to use a SERDES but I cannot use BGA chips..And since I need multiples using externals takes too mch PCB space. This could be an option for the OP if only one is needed.

Regards Thomas

Yup, it's the CY7C994 IIRC. I do not have the datasheets at home. There is a part that goes up to 200MHz.

Yup, but I need to OR the output of different FFs. But maybe an external gate could be an option.

It is only the difference of the different paths.