Microcontroller with I2C AND robust clock stretching?

Do you have a question? Post it now! No Registration Necessary

Translate This Thread From English to

Threaded View
Does anyone know of an 8-bit microcontroller (among PICs, 8051s,
MC68XX, Atmel) that has a built-in i2c module which does the following:

** As a i2c slave device, it's module automatically stretches the i2c
clock (SCL) during both a WRITE and a READ by the master?

(I currently am using PICs, and clock stretching does not automatically
occur when the master does a WRITE. Thus I have a bit of a dead time
where the master can quickly issue another write, resulting in an
overrun. Thus it is up to the master's software to delay itself between
successive writes.)

Thanks,
Mike


Re: Microcontroller with I2C AND robust clock stretching?

Quoted text here. Click to load it

This is a slightly unusual request.
Normally, clock stretch was used for the simplest bit level slaves, with
SW layers that needed to slow down the master. - see the Philips LPC7xx
series for bit-level i2c examples.

  Once you have Byte level i2c, then clock stretch is less relevent, and
most such systems ( eg Serial EE memories), work by ACK/NACK to signal
busy. That way, you do not lock up the whole i2c bus with a slow system.
  Most modern uC have no problems keeping up with byte level i2c
transport, even up to ~ 1MHz.
-jg


Re: Microcontroller with I2C AND robust clock stretching?
The 16F876 PIC would only clock stretch on a read.
The updated 16F876A clock stretches on both read and writes.

Quoted text here. Click to load it



Re: Microcontroller with I2C AND robust clock stretching?



Quoted text here. Click to load it

Assuming you are not using SM Bus:  If the Slave does not ACK you can not
assume reception and need to retransmit until you get the ACK.  You can
also try to have the slave force the clock low after the byte is received.
The Master will be forced to wait.



Re: Microcontroller with I2C AND robust clock stretching?
Thanks guys.

Regarding comments that the Master should check for ACK with each byte,
doesn't an ACK by the slave merely tell the master that the byte was
received? However, if the slave microcontroller's isr does not run in
timely manner (for example, if other isrs are running), then the only
way to inhibit the master would be to stretch the clock.


Site Timeline