Selecting Mosfets for Lowest Power Dissipation

I found this: Taken from

"Once you have narrowed the choice to a specific generation of MOSFET based on cost (the cost of a MOSFET is very much a function of the specific generation to which it belongs), select the device within the generation that will minimize power dissipation. This is the device with equal resistive and switching losses. Using a smaller (faster) MOSFET increases resistive losses more than it decreases switching losses; a larger (low RDS(ON)) device increases switching losses more than it decreases resistive losses."

Neat.....50 50 on the losses...

Rough formula for switching loss:. Pdswitching = (Crss x Vin^2 x fsw x Iload) / Igate (Igate is the MOSFET gate-driver's sink/source current at the MOSFET's turn-on threshold (the Vgs of the gate-charge curve's flat portion).)

How much does Crss vary among mosfets? What a PITA...I also have to estimate Igate.. Once I solve for Pd then I can calculate the corresponding Rdson.. Then I have 2 specs to pick a mosfet out of a table of mosfets.

Am I on the right track? Shortcuts?? Is there an app where I just fill in the blanks and it just spits out a part number? :) D from BC

Sounds not so bad. Generally spoken, newer devices have lower losses (=smaller chip inside).

I use LTspice to run efficiency calcs. It's easy. Use digikey to find what is buyable.

I don't understand how Mot comes to the 50:50 rule.

- Henry

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"D from BC" schrieb im Newsbeitrag news: snipped-for-privacy@4ax.com... | I found this: | Taken from |

| "Once you have narrowed the choice to a specific generation of MOSFET | based on cost (the cost of a MOSFET is very much a function of the | specific generation to which it belongs), select the device within the | generation that will minimize power dissipation. This is the device | with equal resistive and switching losses. Using a smaller (faster) | MOSFET increases resistive losses more than it decreases switching | losses; a larger (low RDS(ON)) device increases switching losses more | than it decreases resistive losses." | | Neat.....50 50 on the losses... | | Rough formula for switching loss:. | Pdswitching = (Crss x Vin^2 x fsw x Iload) / Igate | (Igate is the MOSFET gate-driver's sink/source current at the MOSFET's | turn-on threshold (the Vgs of the gate-charge curve's flat portion).) | | How much does Crss vary among mosfets? | What a PITA...I also have to estimate Igate.. | Once I solve for Pd then I can calculate the corresponding Rdson.. | Then I have 2 specs to pick a mosfet out of a table of mosfets. | | Am I on the right track? | Shortcuts?? | Is there an app where I just fill in the blanks and it just spits out | a part number? :) | D from BC

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Rds(on) and Ciss aren\'t related except that the longer it takes to
charge and discharge the gate capacitance the longer it will take to
turn the MOSFET on and off.  That means that during the time the
channel is in transition it\'ll be dissipating a lot more power than
it will be for the same time when it\'s either on or off.  

Ciss doesn\'t dissipate any power in the MOSFET except in the ESR of
the gate capacitance, but the driver has to source and sink the
charge and discharge current, so there will be some power dissipated
in the driver.

So, what you want to do is get a MOSFET with the Rds(on) you
need/can afford and the lowest Ciss you can find, then drive the
gate as hard as you can so that the MOSFET will turn on and off
quickly.

Using a MOSFET driver will save you a lot of woe, and some good ones
are at:

http://www.micrel.com/page.do?page=product-info/mosfets.shtml

You mean do it like this?... Let's say I can waste 2watts... Then I solve for Rds(on). Then I look at all the mosfets with that Rds(on) and pick the one with the lowest gate charge. Then ram the gate with powerful mos drivers and hope that Vg can rise and fall fast enough to lower switching losses. (Slow operation = heat.) Hopefully the switching loss is not significant compared to the heat from Rds(on).

What I'm looking into is: Given Id, Vd, Igate, freq, duty; does a power dissipation minima exist given a wide assortment of mosfet Rds(on) and gate charges? A sweet spot...

D from BC

chip inside).

buyable.

I know...The rule is strange..

50% heat due to switching and 50% of heat due to Rds(on). It shouldn't matter what combo...2%, 98%....40% 60%...20%80%.... I just want lowest mosfet heat. (Neglecting mosfet driver dissipation)

I could create a table of Rds(on) and gate capacitances based on mosfets available at digikey.. Then run multiple simulations in LTspice to find the coolest mosfet.. Something just seems wrong about this... D from BC

"D from BC" schrieb im Newsbeitrag news: snipped-for-privacy@4ax.com... | On Sun, 11 Feb 2007 12:20:12 +0100, "Henry Kiefer" | wrote: | | >Sounds not so bad. Generally spoken, newer devices have lower losses (=smaller chip inside). | >

| >I use LTspice to run efficiency calcs. It's easy. Use digikey to find what is buyable. | >

| >I don't understand how Mot comes to the 50:50 rule. | >

| >- Henry | | I know...The rule is strange.. | 50% heat due to switching and 50% of heat due to Rds(on). | It shouldn't matter what combo...2%, 98%....40% 60%...20%80%.... | I just want lowest mosfet heat. (Neglecting mosfet driver dissipation) | | I could create a table of Rds(on) and gate capacitances based on | mosfets available at digikey.. Then run multiple simulations in | LTspice to find the coolest mosfet.. | Something just seems wrong about this...

At least the rule must have a function of duty-cycle!

- Henry

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I recently found this at:

"It's surprising to note that at higher switching frequencies, a MOSFET with higher on-resistance can actually improve SMPS efficiency. You must look beyond on-resistance to understand this behavior. "

So...I'm thinking.. Given a mosfet drivers trise and tfall, I just have to get a grasp on how to pick a mosfets Rdson and gate charge. D from BC

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Where?

In the MOSFET? 

In the driver?

Total from the supply?

I've heard of SiC Mosfets with ridiculously low Rds(on) but I suspect it's not available yet.. D from BC

Ooops... should have specified that 2watts wasteable ..in my example.. That would be 2watts = drain|source dynamic heat + heat from Rdson. I'm assuming that mosfet heat is far from the driver heat and is negligible. (D=40%, f=100khz)

I don't know yet if the legwork is worth doing. .. For all I know I could spend hours just to discover the math and compare dozens of mosfets to get that optimum Rdson/gate charge combo and only end up with a minor 10% improvement compared to just selecting the lowest tolerable Rdson. D from BC

I've never hit a sweet spot. I filter on voltage it can cope with, then current, then price, then buy a couple.

10nF, 1nF who cares? those gate C's are really big. Bang 'em with gate driver chips. Only killer is operating frequency. God know why but I spent 2 hours last month with paper and calculator looking at switch losses on a design using a pair of 80A FETs. Bought the FETs and the calculated heatsink, built it, run fine. Within 5 minutes and for other reasons I'd changed the design to a higher Frequency and a different switching arrangement. Those 2 hours now lost for all time. Lesson learned was don't waste valuable time with the sums, just select on price and keep an eye on the spice.

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Interesting... Are you saying that it's so complicated that hit and miss determination is the faster method. Just pick the essential mosfet specs and then compare in spice..

Select on price...Eye on spice Nice electronic poetry... :) D from BC

If you look at the Rds losses and the gate capacitance losses you'll realise you can calculate the whole lot dead easily. Then as you're doing that you'll realise it depends not only on the frequency but also upon the "on time" of the fet. So you can calculate the losses only as long as you know the average on time. eg on time = 100% = no gate capacitance losses and Rds is dominant. On time = 1% and Rds becomes almost irrelevant and the switching losses dominate.

The Mot rule of Rds losses = to G cap losses works quite well when the the average on time is 50%. But it's only a rule of thumb to give you a starting point.

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Gibbo

This email address isn\'t real.

Yep...I got my eye on the duty... For a given mosfet driver, it seems like this: For low duty, then pick low gate charge to reduce Vds transient time. For high duty, then pick low Rdson to make an efficient switch.

I just want to clarify that Mot rule.. (Also..what is Mot? Motorola?) Is it... Rds pwr = Drain/Source transient switching pwr (or on/off state change power) Or Rds pwr = Drain/Source transient pwr + gate drive power required D from BC

Correct.

Yes. Just an abbreviation I used which I think appeared earlier in the thread.

Yes. But the losses increase depending how well the driver operates obviously due to drain/gate capacitance. So both are related.

No that is added in separately.

I've read some of your posts so I know you're not daft.

Imagine trying to switch on a mosfet with a 1M source impedance. The falling drain voltage would (due to drain/gate cap) hold the gate low for [comparatively] ages thus increasing the switching losses (negative feedback). Effectivley the gate drive would be slow so the drain voltage would fall slowly (thus increasing normal mosfet losses). But you already know this.

I imagine gnome knows all the formulae. Try a new thread with smps in the title :)

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Gibbo

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dont forget when comparing FET Rdson to pick some Tj other than 25C. different FETs have different Rdson-vs-Tk curves. I always normalise to

125C and go from there.

Cheers Terry

Damned fine point with mosfets.

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Gibbo

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(I'd missed that. Maybe before sending, I should read the stuff :).

Yes, let spice do the grunt work as your servant, while you figure the overall strategies. It's not that the FET usage is complicated, it's more that's it can be tantalisingly easy to sit down and spend time doing a complete 'carved in Granite' electrical/mechanical FET design on paper, building it and then finding real world 'minor' factors need taking care of that could only have turned up in some long winded tolerancing episode. E.g fitting some readily available value for a clock cap' moves the FETs and (say) switching inductors into occasional discontinuous cycles. john

John I'm still trying to work out how to contact you by email. Have you done a seacrh on jjdesigns? Quite amusing really.

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Gibbo

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