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Lowest power RAM

Hi,

What kind of RAM can be used with the lowest power available, with an MCU that might run either at 15MHz or 1MHz, possibly both? The chip is LPC2210, which allows 8,16,32-bit wide data busses and can do SRAM, DRAM or EDO. I'm not worried about the cost or speed. The ram will also be underclocked to match the MCU, and also to lower power requirements. I'm hoping for under 1mA @ 3.3v or less, for 1M x 8. What kind or make of memory should I use?

Ive seen The cellularram chips, but like most other DRAM the difference between active and standby is big, and I dont know how to calculate the average usage @ 1MHz. Surely there'd be hardly any activity on the ram for the most part at that clock... can I safely say the usage will be under 1mA even with a memory intensive app running on the MCU @ 1MHz?

Can I have some sort of SRAM that can give me lower power usage?

Since I'm underclocking, the signals to the ram chip will be running much slower. But the fraction of time the activity pin is high will remain the same (thus the power usage on sram). Can I somehow (with capacitor and high speed latch tricks or otherwise) reduce the active high state on the sram such that a 133MHz sram read at 1MHz will only see the active high at 1/133rd times the normal?

Lastly will using the 8-bit wide data path for ram chips significantly lower power consumption compared to the 32-bit wide data path?

Reply to
ghazanhaider
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The LPC2210 memory controller doesn't support DRAM or EDO, only SRAM (and burst ROM). Low power SRAM, made by Samsung and others, looks like the best fit.

The K6X8016T3B family (512K x 16, VCC=3.3V) for example have a standby current of 15uA (CS inactive), and max 3mA when reading at 1 Mword/sec. If you can keep it inactive most of the time, you'll get well below 1mA.

If you need to do four times as many cycles, 8-bit data means more power.

Karl Olsen

Reply to
Karl Olsen

First, a SRAM that is not chipselected only draws standby current. Second, 4 8 bit chips beside each other also make a 32 bit datapath.

Rene

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Reply to
Rene Tschaggelar

I'm sorry. By 'active high' I meant chipselected. Is there a way to pull a chipselect low for a larger fraction of time, on an SRAM chip if the MCU is underclocked?

"Second, 4 8 bit chips beside each other also make a 32 bit datapath"

I know. However my MCU allows 8-bit data paths as well.. for say 1Mx8. The question was, will using fewer traces make a significant dent in the power usage?

Reply to
ghazanhaider

The controller does whatever is necessary. You just have to make sure that unused RAM is not unnecessarily chipselected.

It just makes 4 times as many access. You won't gain much by using an 8bit wide bus in terms of power.

Rene

--
Ing.Buero R.Tschaggelar - http://www.ibrtses.com
& commercial newsgroups - http://www.talkto.net
Reply to
Rene Tschaggelar

Thanks guys. It helped. I'll use 32-bit wide data paths, and will look for 256Kx32 to use, else 2x 256-x16 chips to keep chipselect low.

Will using PSRAM or an external dram controller help lower power usage further or is it not worth it?

Reply to
ghazanhaider

DRAM or SDRAM use much more power than SRAM. Check out the Samsung datasheets.

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Karl Olsen

Reply to
Karl Olsen

Have you done any analysis of the distribution of RAM access for 8, 16 and 32 bit variables (both read and write) ?

If the RAM access is predominantly 32 bit, then 32 bit wide paths would make sense.

However, if you have a lot of 8 or 16 bit access, the situation can be quite different. In 32 bit memory mode, does the processor have four separate chip selects for each of the bytes in the 32 bit word ? In this case the non-selected bytes would not consume any extra power during read.

How is 8 or 16 bit writes implemented in the 32 bit system ? Are there four separate chip select or write enables for each byte ? If not, a

8 or 16 bit write would require a 32 bit read, modification of 8 or 16 bits by the memory controller and write back of the whole 32 bit memory word.

At least some old DRAM systems required quite a lot of average power (mainly due to frequent refreshes) when the system was required to operate at high temperatures. Check for the requirements on current products at extreme temperatures.

Paul

Reply to
Paul Keinanen

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