Selecting Mosfets for Lowest Power Dissipation

After reading the book "Switching Power Supplies A to Z" by Sanjaya Maniktala, I derived the following expression for the switching loss (Pm) in the Miller region. All the parameters can be found on a typical mosfet data sheet.

//Back-of-envelope calculation of Miller-plateau crossover loss. //The Miller loss omits the loss as the drain current swings at VDS=Vin constant. //The Miller loss is the largest switching loss which occurs as VDS swings at IL constant theta=Qgs/(Qg-Qgd);//Ubiquitous gate-charge factor appearing in Miller loss formula Pm=(IL*Vin*Qgd*Rdrive*f/(2*Vdrive))*(1/(1-theta)+1/(theta-Vsat/ Vdrive)); where, //Parameters (SI units) f=500.0e3;//Switching frequency Vdrive=4.5;//Gate driver voltage high voltage Vsat=0.0;//Gate driver logic low voltage Rdrive=2.0;//Lumped drive impedance plus mosfet gate resistance Rg Vin=15.0;//Input voltage for the buck VDS(t=0) for all topologies IL=22.0;//Free-wheeling diode current //Mosfet parameters at a typical VDS Qg=36.0e-9;//Gate charge factor Si4442DY, VDS=15V, VGS=4.5V, ID=22A Qgs=8.0e-9;//Gate charge factor Si4442DY, VDS=15V, VGS=4.5V, ID=22A Qgd=10.5e-9;//Gate charge factor Si4442DY, VDS=15V, VGS=4.5V, ID=22A

Stephen

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stebla
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So...the switching loss calculation includes Qgd, Qgs and Qg...or in other words, every pin to pin capacitance.

Like someone posted... I'm probably going to select a bunch of mosfets with the right Vds and Id ratings. ( Price will be a factor at some point.) Then try'm all in LTSPICE. (.step mosfetlibrary 1 100 1???)

Reply to
D from BC

I'll try again. (3rd attempt) Don't know what the f**** happening to the stuff I send but about 6 posts have gone AWOL over the past week including a hand crafted long nasty rant about FPGAs. :) Never mind. It's ...

john.jardine (the "at" symbol) idnet.co.uk

As an internet device, the "jjdesigns" was bought up in the early days by a landscaper and dress maker. Watching how this week's been turning out, I'd probably been better off also following some nice, uncomplicated, detail free, stress free, son-of-the-soil type activity :)

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Reply to
john jardine

The 'total gate charge' spec includes Crss effects on the duration of the gate voltage plateau during switching. Unfortunately this is usually a 'typical' value, at a nominal drain starting voltage.

Keep in mind that you may not be permitted to witch things as fast as you might want, simply due to the excess noise it may generate in dependant rectifiers - decoupling these effects with series limiting elements (beads and such) may be a worthwhile study in a functional breadboard.

Depending on the budget, methods of assisted switching or zero-voltage topologies could prove effective at battling noise or temperature rise.

RL

Reply to
legg

After someone posted a formula I found:

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So I did some estimates instead of a bunch of spice simulations...

Input data: Vd= 270V Id= 2.4A Idriver=2A f=100khz D= 40%

All these Digikey stock parts have about the same total power loss.. FCP20N60 FDH44N50 FQP9N50 FCB11N60 FCB20N60 FCP7N60 SPA08N50C3 SPA12N50C3 SPP16N50C3X

From the above: Qg(total) ranged from 18nC to 90nC and Rdson ranged from 0.11 to 0.73 ohms.. The winner at an estimated 2.4Watts is Fairchild's Superfet at Qg(total) = 40nC and Rds(on) =0.32ohms..

So...I could run the math again with a more powerful mos driver... (Micrel was mentioned with 6A peak drive current.)

Or.... I'm wondering about paralleling mosfets..... Maybe I could parallel a bunch of speedy low charge mosfets until the conduction losses are minimal. Is this practiced in smps design? Does this explain those seemingly useless high Rds(on) mosfets? D from BC

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D from BC

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