NAND Flash Datasheets needed...

Heh, you won't be able to buy any decent NAND flash unless you buy >100k pieces, so you don't need datasheets anyway.

You have to contact manufacturer directly.

Vladimir Vassilevsky DSP and Mixed Signal Design Consultant

What exactly do you want? USB thumb drives and SD memory cards have little microprocessors in them that greatly simplify reading / writing the devices. Do you need the R/W process, or are you trying to do something that results in the process "getting in your way"?

If the former, I do have the info on another PC, but didn't want to bother if it's not what you needed. If memory serves (no pun intended..) you can go to the SanDisk web site and follow some links there and that will take you to the R/W info that I think you're looking for. (?) Or Google for the relevant terms.

If you just want to R/W nand flash, any manufacturer's data sheet should provide that info. Try Digikey.com they usually have links to the datasheets.

Good luck in any case. It's pretty complicated stuff, even with all the uPC bit-level dirty details being done for you.

-mpm

I want to synthesize my owh CPU core that could execute code directly from NAND flash, much like conventional CPU fetches program from RAM into a cache and executes it. To do that, I have to be intimately informed about chip protocols and timings and I can not have any intermediate logic. Such system shouldn't have to load program from nonvolatile media but could execute it on media itself.

I have seen USB keys faint ( as in get stuck in some state, start blinking violently and stop working until replugged) and die just from R/W access ( albeight intense ). Logic on these things does not like many non-linear writes, especially when interspersed with many non-linear reads and I can not predict its behaviour under these conditions.

I need exact specs for a concrete chip in production that I can byu, not principle explained in some document.

That's my point. I've searched around and couldn't get to ANY datasheet about NAND FLASH. They are either inacessible or one has to prettyplease manufacturer and sign NDA - which I tried and got no answer.

Thanks.

Not really. I've managed to Google-out ( =3Dmodern sinonim for fish- out ?) datasheet for Micron's old 2Gb model and it's a breeze. I like it much better than having to arm-wrestle with extra logic...

But Micron has its representatives here AFAIK. And I have had no troubles before when snooping around for fast serial Flash ( like the ones for BIOS on new motherboards), for example.

O.K. I'll give it a go.

It is not possible to execute directly from NAND flash. NAND flash is block access device, a lot like, say, a hard drive. Booting from NAND flash is fairly standard procedure though; it is not too different from booting from any other media.

All logic that you need to access NAND flash is a simple parallel port.

How?

I have the datasheets, but I can't give them up.

Vladimir Vassilevsky DSP and Mixed Signal Design Consultant

Why not ? I could boot from my serial configuration FLASH that I use to configure FPGA. If I have the liberty of making the CPU core and its periferal logic, whoy shouldn't I be able to make a CPU core that is able to load a page before it jumps on code in it ? After all, modern CPUs behave similarly. When jou jump to some location that is not in cache, CPU doesn't access the memory just for that location, it loads whole cacheline and if predictor thinks there is aq good chance you'll need more data, it loads subsequent one too...

Here it is just a matter of making a logic that is capable of preloading ( at least parts of) FLASH pages...

As said, one way could be to do what current systems do when they try to access the area that has no TLB entries- no real memory backing. CPU detects this and generates exception, during which it loads the page into some buffer/cache and then resumes processing.

Or, it could be sole repsonsibility of the user to make sure that page is loaded into internal buffer/cache before using it.

Or some inbetween scenario, or...

"predictor" --> cache prefetcher

Because the raw NAND flash is not a chunk of addressable memory, but a block access device like HDD or CD.

This is what boot process is about.

Yes, you can make block device behave like memory for the cost of tremendous overhead. What is the point?

Look at the description of the NAND flash controller of AD Blackfin-527 CPU. It has protocols and timing diagrams.

Vladimir Vassilevsky DSP and Mixed Signal Design Consultant

I don't see where is that "tremendous overhead". You need a couple of clocks to adress desired page and then maybe extra couple to get to desired location on the page.

Which is almost exactly the process as it goes with SDRAM, for example.

It is true that FLASH works at lower bandwidths and clk frequencies than DRAM, but:

- not every application needs very high speed clocks

- there are new NAND FLash components with "high speed" ( well

- as with RAM, you pay latency just for the first access. Once data is cached, alll reads go at full speed

- this way, one can have practically all the code accessible instantly and use RAM just for R/W data

I can think of many applications that could use such arrangement very well...

Tread ~ 50uS.

~1000 times slower then SDRAM.

But.

I can't think of any useful application.

Vladimir Vassilevsky DSP and Mixed Signal Design Consultant

I didn't know that - didn't have a datasheet.

It seems that it is the consequence of NAND Flash structure and that there is no real addressing, but internal electronics shifts the state until content of desired cells end up in data register. This could mean that Tread access time varies according to the realtive position of desired block to the position of one that has been just read. Which means that reading adjacent or blocks that are ascending and close should be relatively fast.

But even worst case seems worthwile, at least for some applications...