better 4046 PLL

Neeerp! You're the moron. BJT (or diode) models don't slow simulations... Berkeley-based simulators are designed specifically to handle such models. What slowed your simulation was likely a poorly constructed behavioral model. My guess would be the use of the (hard) LIMIT function... I see that a lot in amateurish modeling efforts.

And I don't know how many times I've seen poorly constructed behavioral models (or "ideal" diodes :) hide defects in a design.

You just have to be so-o-o-o technical and name-call and name-call. You're clearly an amateur when it comes to understanding and using a simulator.

It shows... or more accurately, as JK showed you up ;-)

I did a whole chip simulation last night... 155 devices (MOS), admittedly a small chip as my chip designs go, but absolutely no behavioral devices, video DC restore and (UTC) data recovery, actual video signal... took about 5 minutes.

BTW: "Iterating" is hacker's terminology... can't calculate/design, then "iterate" ;-)

You never fail to. But you're so wonderful... you just can't avoid demonstrating your manic-depressive (and associated superiority-inferiority) complexes over and over and over...

Designed anything properly recently... or do you just cover your failures with supposed alternate "analyses"... and "iteration" ?>:-} ...Jim Thompson

I never said that they do; John K did, about the SMS7621. Argue with him.

In other cases, I've had transistor-level models seriously slow down a sim, enough to be inconvenient.

What slowed your simulation was likely a poorly

If someone doesn't undestand a circuit, and *has* to simulate it, then every device model must be fully accurate; good luck with that. If you understand a circuit and, say, just want to tune loop transient response, simplifications are fine and save time.

I don't simulate a lot: I design. It's a different process. Since I don't live by simulation, I'm not as familiar with Spice as people who simulate constantly.

We've sold megabucks of gear with our PLLs inside. They all work.

You can't help turning technical posts personal. You can't help, period.

Just recently?

Several multichannel ARBs

Several laser drivers, some picoseconds, some hundreds of amps

VME digital i/o board

Parts of a couple of PCI Express controllers.

Bunch of picosecond timing and fiberoptic things

Controller and several i/o boxes for an EUV lithography source.

Another NMR gradient driver

Another magnetic field mapping system

All stuff that you couldn't do.

or do you just cover your

They all work. People are buying them. No technical failures, except that not everything always sells.

In my career, over a thousand PCB designs, I've only done a couple that were technical "failures." They could have been fixed, but the customer went away first. One was a tugboat alarm system that had intermittent CMOS latchup problems, before I knew about CMOS latchup. One other was a microstepping driver, problems with the H-bridge power stage caused us to miss the boat. Both decades ago. But there's no serious money in either business, so no loss to anything but pride.

I don't know how many times I've said, I usually design by doodling on paper, then verifying by simulating all process corners.

But I guess your superiority complex says that only you design and everyone else is helpless without a simulation?

Those of us who can't go back a tweak a board... silicon is like cast in concrete... simulate all "construction" possibilities.

As an amateur in simulation you ought to be careful criticizing what you don't understand.

Do they work as well as they could, or only as good as you iterated but didn't move the right variable?

Do you have any idea how ridiculous that statement sounds? You used terms like "moron" and "Have I mentioned lately that you're an idiot?" in response to my technical issues.

Anything you "built" that has ECL/PECL or LVDS in it... I probably designed the chip that you are using. And who knows what other chips... I've designed so many I lose track of all the functions I've done.

Whoopee doooo >:-}

But you're so wonderful... you just can't avoid demonstrating your manic-depressive (and associated superiority-inferiority) complexes over and over and over... ...Jim Thompson

The op amp doesn't have to follow the transient. That's what the capacitor is for.

I wouldn't call that a revelation. It was about the second PLL I ever designed, back when I was about 21 and had been chucked into the deep end--my first engineering job (with my brand-new B.Sc. in Astronomy and Physics, plus a 10-year hobby background) gave me sole responsibility for most of the timing and frequency control system for the first commercial direct-broadcast satellite system (SpaceTel from AEL Microtel, introduced in 1983). I'd heard of PLLs at that point, but never actually seen one, let alone built one.

Very educational, and (between periods of panic) great fun as well. (Also pretty sporting on Microtel's part.)

And LCs don't have phase memory either--they obey a differential equation, so there's no memory. If you dump some charge onto the tank cap, unless you do it at the voltage peak, you'll change the oscillation phase.

A dead zone makes the PLL more or less useless all by itself, but you can fix it by pulling the PFD a few nanoseconds off the zero point--usually something like a 1M resistor to ground from the PD2 output is all you need.

Nope. A SAW resonator, sure, but not an LC. By tuning the varactor, you can change the instantaneous frequency of the LC in a time much less than Q/f0, precisely because it has no memory. Systems with memory require integral equations to represent them, but differential equations relate instantaneous quantities.

That works for mechanical systems too--a friend of mine from grad school, Tom Albrecht, sped up the response of atomic force microscopes by a factor of about 100 by running the cantilever as an oscillator, and looking at the FM caused by the presence of the sample. The force gradient looks just like a change in the spring constant, so the resonant frequency responds in much less than 1 cycle. If you do it the old way, by using a constant excitation frequency and looking at the amplitude and phase of the cantilever's response, you're stuck with the Q/f0 speed limit.

Cheers

Phil Hobbs

Yup. You have to put a bit of time delay in the model if the loop is going to be fast, but that's the only real subtlety. (It's a quarter cycle for an XOR and half a cycle for a PFD--the average time before a phase perturbation can show up in the PD output.) The nonlinear dynamics aren't quite captured by this, but it's pretty close.

I've sometimes used a 4046 as an acquisition aid for a diode-bridge phase detector. You typically need to generate the quadrature phase anyway, for a decent lock detector, so you just run the 4046 off that. (I generally use divide-by-4 Johnson counters, like most other folks.)

Then the 4046's PD1 is the lock detector, PD2 is the acquisition aid, and the diode bridge does the actual work.

The other cute method for acquisition is to put a little positive feedback around the loop integrator. When the loop is out of lock, the phase detector gain goes to zero, so it makes a (very) slow triangle wave sweep of the whole VCO tuning range. When it goes through the right frequency, the phase detector takes over and pulls in. (I thought I was the first to use this, in 1981, but later discovered it had been invented by somebody else a few years earlier. Cute circuit, regardless of whose it is.)

Cheers

Phil Hobbs

Phil, Your talking of dealing with an analog input signal, correct?

There was some scheme called (IIRC) "tanlock" that gave a wider range and better acquisition, but I can't find my book at the moment :-( ...Jim Thompson

There aren't that many knobs to turn in a PLL. You get the damping right and optimize the loop bandwidth for minimum phase noise or jitter. Those things are done by design, not by simulation. We don't usually care about acquisition time, which can involve some truly intimidating math.

I never said that you can't, or haven't, designed working linear ICs. You keep saying that I can't design board-level electronics, which is idiotic.

VCXO loops are inherently slow, so a couple of clocks in an FPGA will be pretty much invisible. Most VCXOs have an (often unspecified) RC lowpass filter before the varicap, low 10s of KHz modulation bandwidth typical. Loop analysis should take that into account, too.

The PLL we use in our digital delay generators drives an LC oscillator that tunes very fast. We need it to lock to within picoseconds in a few hundred ns, tens of cycles. I simulated that in PowerBasic, with all the delays. There are ADCs and DACs in the loop, and algorithms, so it would be awkward in Spice. Maybe something like Matlab would work.

With an FPGA (and a VHDL jock), you can do all sorts of cool sweep-search things.

Well, duh! Posted here _10_ years ago...

I've been doing such analyses since I was a kid.

You forget I spent quite a few years doing "box" designs for GenRad (and others). "Analog" is quite an encompassing art form. I even designed a 5V/400A switching power supply once ;-)

I didn't say you couldn't. Where you get that idea? But you certainly can't cope with any criticism, and switch to name-calling and your standard crap line... "What have you designed recently?"

Do us all a favor and grow up. ...Jim Thompson

I remember that one--it used an analog divider or something to stretch the sinusoidal PD output into a more sawtoothy sort of thing. I remember reading about it in Gardner but never used one. It was easier to use trapezoids (really clipped sinusoids) going into the diode bridge, which gave almost exactly the same effect.

Cheers

Phil Hobbs

Ok, the digital version:

Sorry for Amazon.de, but Amazon seem to know me.

The book covers the "normal" tanlock loop, but it is really about a version that replaces the Hilbert transformer by a cheap delay and seems to live quite well with the resulting imperfections.

IIRC, the main advantage of the tanlock loop was a certain insensitivity to input level variations. Since I had AGC anyway, I did stay with more mainstream PLLs/Costas etc. (And since I had a DDS upstream, sin + cos came nearly for free and the Hilbert was no problem.)

regards, Gerhard

The Amazon pricing is funny: the cheap used pocket book costs most.

:-)

It wasn't an attempt to improve the speed. What happened was that John L's simulation ran reasonably fast for him, but stalled for me. It turns out that John has been using a model for the 7621 that isn't the official one. I was using the Skyworks-supplied model, with a BV of 3 volts, which just breaks down with the reverse voltage it gets in that circuit. Substituting a diode with sensible reverse breakdown for the application made things run fine.

The SMS7621 is a perfectly good *2 VOLT RATED* mixer diode, and the official model is good in Spice, when it's used within its ratings.

I've not seen John's 7621 model ,but I'd like to. He claims to use it up to 8 volts, but that's way out of ratings.

It isn't, of course.

It's the BV that caused the problem. I've just noticed that none of the LTspice-supplied diode models have breakdown voltages - apart from those characterized as zeners. UGH!

Moral: use manufacturer's models.

As to behavioral models, what really screws things is people trying to extrapolate fitted polynomials into no-man's-land.

Yep. LTspice plays fast and loose with models that speed things up, hide instabilities, and are rarely more than sloppy approximations to real life. But it's fast ;-)

Thus my many posts/inquiries on the LTspice list regarding smooth fits.

Right now I pretty much make TANH-based bounding functions, but I am investigating "splines".

I suspect our resident "expert" designer is being had by PhD modeling jerks who use the LIMIT function without regard to the consequences ;-) ...Jim Thompson

The "model" probably makes it to 8V, nevermind reality ;-) ...Jim Thompson

Nice thread! (I'm enjoying it much more than politcial..stuff.) So, I've never done a PLL, but lots of control loops. The dead band reminds me of the cross-over error you run into if you've got a push-pull power stage in the loop. (There's some place the thing might 'wig out' if set too tightly.) (Class A is my only solution to crossover.) George H.

The actual reverse current is about 1 uA at 4 volts, 5 uA at 6 volts. These kinds of diodes don't have a hard knee... they just leak more as reverse voltage goes up. I use them up to 3.3 volts or so, no problems. I wouldn't use one at anything like 8 volts; it would be very leaky.

In my little self-charging schmitt soft-start, the diode never sees more than about 1 volt reverse, essentially the schmitt hysteresis voltage.

You've said it many, many times. It's clearly stupid.

This is just one of your quotes, in this very thread:

--------------

You said, in another post, "It take some actual skill to design a PLL."

So show us something technical about PLL's... something other than your standard drivel.

You can't. You're a fraud.

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And I did post my diode-error amp/delta-sigma thing, you idiot.

But you

It's a reasonable question to ask obnoxious lurkers who pop up with off-topic trash. They usually don't/can't answer.

This is an electronics design group.

As usual, we have technical discussions and you break personal/obnoxious. You did it here again.

Excellent, I wanted to say this but didn't know how. If you change something in an LCR circuit the change shows up right away. (I'm still getting use to this idea.) So injecting charge at the voltage peak just means the amplitude of the next cycle will be bigger. And it takes ~Q cycles for the transient to die down. (?correct me if wrong?)

George H.