Hi,
I'm having trouble understanding the 4046 PLL data sheet. I want to lock on to a frequency of 200KHz and remain locked between 150KHz and 250KHz. From the data sheet I worked out I needed:
C1 = 100pF R2 = 100K R1 = 66K
But when I try these components the frequencies are much higher.
Can anyone tell me what I'm doing wrong? The data sheet can be seen here:
I'm using 2.b on page 9 with:
Fmin = 150KHz Fmax = 250KHz
Cheers,
Your choices don't look far off, but I would read the graphs this way. With a 12 volt supply (interpolating between the 10 volt and 15 volt supply lines), 100k for R1 and 100pF gives a minimum frequency from Fig 8 of about 200kHz.
So R1 should be increased to about (200kHz/150Hz)*100kOhms=133kOhms. I would increase that a bit to cover any capacitance tolerance and stray pin capacitance. Say, 140kOhms.
To get the maximum frequency guaranteed to go above 250kHz, the parallel combination of R1 and R2 need to be less than (150kHz/250kHz)*R1=0.6*R1. I would go 10% lower, in case the cap has the opposite worrisome tolerance. So .9*.6=.54
..54*R1=1/(1/R1+1/R2)
75,600=1/(1/140K+1/R2) R2=164kOhmsSee if something nearer to to these values work better.
Are you using a HEF4046 or is it a 74HC4046?
Sorry I should have mentioned that in the post. I'm using the HEF4046 with a 12V regulated supply.
Have something to add? Share your thoughts — no account required.
Ask the community — no account required