We sure do! We embedd a deadband-free version inside FPGAs all the time. We don't use a charge pump, but a pair of hard logic outputs, into a dual schottky diode and an RC or opamp.
--
John Larkin Highland Technology Inc
www.highlandtechnology.com jlarkin at highlandtechnology dot com
Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators
Custom timing and laser controllers
Photonics and fiberoptic TTL data links
VME analog, thermocouple, LVDT, synchro, tachometer
Multichannel arbitrary waveform generators
I didn't contribute to the circuit, I just told Ron, "Here's what I'd like it to do..."
I can round up Ron to verify that, if you're out to make an issue of it. ...Jim Thompson
--
| James E.Thompson | mens |
| Analog Innovations | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| San Tan Valley, AZ 85142 Skype: Contacts Only | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |
I love to cook with wine. Sometimes I even put it in the food.
And in many of my custom I/C's, even in a recent chip that measures soil moisture ;-) ...Jim Thompson
--
| James E.Thompson | mens |
| Analog Innovations | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| San Tan Valley, AZ 85142 Skype: Contacts Only | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |
I love to cook with wine. Sometimes I even put it in the food.
Correct. I told Ron what an ideal PFD would do, but had no clue about how to do it... at least back then... my current bag of tricks includes how to do it when there are missing edges.
I didn't invent the circuit... just like your customers who come in and ask for a box to "do so and so" didn't design the your box. ...Jim Thompson
--
| James E.Thompson | mens |
| Analog Innovations | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| San Tan Valley, AZ 85142 Skype: Contacts Only | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |
I love to cook with wine. Sometimes I even put it in the food.
Deadband comes from the analog charge pump, and not the digital logic portion. When you are on time, the narrow pulses won't go through the charge pump so there is no correction. When you have a small time offset, the pulse widens and starts to go through the charge pump so you start to get correction.
The op amp is unlikely to be fast enough to follow the narrow on-time pulses, so you probably are getting deadband. But crosstalk to the vco can injection-lock the oscillator to the reference and make it seem you have no deadband.
I use switchable current source and sink in most of my PLL's, with an external resistors for accuracy, if I can convince the customer ;-)
The best game is to have one external resistor set a master current reference... then everything is ratiometric internally, and absolute values (+/- 25% on-chip) don't matter nearly so much. ...Jim Thompson
--
| James E.Thompson | mens |
| Analog Innovations | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| San Tan Valley, AZ 85142 Skype: Contacts Only | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |
I love to cook with wine. Sometimes I even put it in the food.
It's not hard to make the charge pump UP and DOWN blips overlap a little, eliminating the deadband. In our voltage-output version, we also overlap a little to kill the deadband. That increases the loop gain by 2:1 in the narrow overlap region, no problem if you plan for it.
FPGA outputs aren't ideal for charge pumping; the tristates are slower paths than the logic levels, and the pullup/pulldown currents are vaguely defined. A dual diode and a couple of resistors fix all that.
Well, no. Charge is still conserved. The diode current has to go somewhere.
The opamp is slow, like kilohertz closed-loop bandwidth in a 100 MHz PLL. We generally plan for the PLL bandwidth to align with the VCO 1/f phase noise corner, to pick up control where we need it. That minimizes jitter.
But crosstalk to the vco can
Well, no.
--
John Larkin Highland Technology Inc
www.highlandtechnology.com jlarkin at highlandtechnology dot com
Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators
Custom timing and laser controllers
Photonics and fiberoptic TTL data links
VME analog, thermocouple, LVDT, synchro, tachometer
Multichannel arbitrary waveform generators
The deadband does not occur in the digital logic. Deadband occurs in the analog portion that follows the phase detector, when it cannot respond to the small pulse widths around zero.
The sample terminates when both latches are clocked. The NAND feedback starts when the signal from both latches has propagated to the output.
The output is applied to the latch resets. Both latches start to reset, and the NAND is no longer satisfied. The reset pulse goes away when the result has propagated through the NAND. The reset pulse width is twice the propagation delay through the loop.
During the reset, both latches are turned on. The UP and DOWN blips are both on and theoretically cancel at the junction of the resistors so there is no net signal to the op amp.
The problem occurs when there is a small time error around zero. If the op amp does not respond, then the output to the VCO doesn't change. This means time small errors are not corrected, resulting in deadband.
Adding delay to the phase detector reset increases the overlap. During this time, the UP and DOWN blips cancel at the junction of the resistors. There is no output from the phase detector, so there is no input to the op amp.
The problem occurs when there is a small time error in the input signals. The Up and DOWN blips no longer cancel at the beginning. This creates narrow pulses to the input of the op amp. The result depends on how the op amp responds.
[...]
That's the problem. If the op amp overloads, the feedback through the loop filter is lost. Charge is no longer conserved.
That slow op amp means it won't respond well to narrow pulses around zero.
Well, yes.
RC oscillators are very easy to injection-lock. It is much harder to injection-lock a LC oscillator.
Phil had a revelation recently about using RC oscillators compared to LC oscillators in a PLL. From his post on Tue, 25 June:
The problem with an RC oscillator is it has no phase memory. You can change the phase instantaneously. A small amount of crosstalk can cause a step change in the phase of the oscillator.
This means the PLL loop now has an error, which will drive the oscillator back to zero error. It returns to the spot where it got in trouble in the first place, and crosstalk drives it away again.
This sets up a limit cycle oscillation, which can be bad enough to render the loop useless.
I have never built a PLL using a RC oscillator that you can't find a limit cycle oscillation somewhere in the loop range. However, it is much harder to do a step change in phase in an LC oscillator, since the tank provides a flywheel effect that remembers the phase of the previous cycles.
So add a little prop delay somewhere to force both the UP and DOWN pulses to be finite width and overlapping a bit at zero phase error. That works whether you use a charge pump or hard UP/DOWN outputs. Tons of people have done it.
If course there's no input to the opamp when there's zero loop error. The real question is: what's the graph of opamp input current versus phase error. The
4046 has a flat spot around zero. Other phase detectors don't.
Why would it overload with a small loop error?
It integrates the mean error current, the sum of all those small pulses. The electrons.
RC oscillators aren't famous for low phase noise or low jitter. Of course use a better, narrowband oscillator, LC or XO, if you want low noise. And use a phase detector with no deadband.
Here's a circuit we've used a couple of times.
formatting link
the up/down blips come from the phase-frequency detector in an FPGA and the opamp output goes to a VCXO. One cute trick is that we can lock the VCXO if we have an external reference, or use it unlocked but calibrated if we don't. In unlocked mode, we turn on U4 to make the opamp amplify (not integrate) and use the up/down signals as a delta-sigma DAC, with value from a cal table in eeprom.
--
John Larkin Highland Technology Inc
www.highlandtechnology.com jlarkin at highlandtechnology dot com
Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators
Custom timing and laser controllers
Photonics and fiberoptic TTL data links
VME analog, thermocouple, LVDT, synchro, tachometer
Multichannel arbitrary waveform generators
The only place you can add delay is in the NAND feedback path.
In this circuit, the overlap width has little or no effect since the UP and DOWN pulses cancel during the overlap.
The pulses into the op amp are large enough to cause internal overload due to the high gain. The result depends on how the op amp responds to overload.
Yes, I'm familiar with your circuit. There is no ripple filter at the input to the op amp. This can create problems around zero phase error when the op amp can't respond to the narrow pulses. The performance depends on the op amp characteristics.
I made a simple PFD and Op Amp analysis circuit for you. The circuit sweeps the phase error from +48ns to -48 ns in 2ns steps. You can zoom in on each sample to see what is happening on that sample. On Time is in the exact center at the 25uS sample.
The parameters for each device are brought out to a spice directive. You can edit the D-flop and NAND speed, and the Gain, Bandwidth and Slew Rate of the op amp by clicking on the desired directive and editing it.
You can see what happens when you change the width of the UP and DOWN pulses by changing the NAND delay. In this circuit, yu will see it has little effect on the op amp response since the UP and DOWN currents cancel each other during the overlap time.
Changing the bandwidth and/or slew rate of the op amp can have a dramatic effect on the response around zero.
You can add the op amp of your choice and see how it responds to the narrow pulses around zero.
I added a ripple filter to the input of the op amp. You can cut the trace from the PD output and connect the filter in its place. You can see it has a dramatic effect on the response of the op amp by reducing the amplitude of the pulses from the phase detector.
All these effects are only to give an idea how an actual loop will respond. They do not include effects such as crosstalk and are no substitute for measurements on the bench.
You will need Helmut's 74HC.lib installed, plus a small text file for the
1n5771 which I supply below.
JK
Version 4 SHEET 1 1260 800 WIRE -176 96 -224 96 WIRE -144 96 -176 96 WIRE -16 96 -80 96 WIRE 80 96 64 96 WIRE 432 160 416 160 WIRE 528 160 512 160 WIRE -576 176 -592 176 WIRE -512 176 -576 176 WIRE -416 192 -448 192 WIRE -384 192 -416 192 WIRE -176 192 -176 96 WIRE -160 192 -176 192 WIRE -688 208 -736 208 WIRE -512 208 -688 208 WIRE -32 208 -48 208 WIRE -160 224 -176 224 WIRE 416 240 416 160 WIRE 448 240 416 240 WIRE 528 240 528 160 WIRE 528 240 512 240 WIRE 544 240 528 240 WIRE 624 240 608 240 WIRE 640 240 624 240 WIRE 672 240 640 240 WIRE -592 256 -592 176 WIRE -304 272 -304 256 WIRE -32 272 -32 208 WIRE -32 272 -304 272 WIRE 80 304 80 96 WIRE 128 304 80 304 WIRE 160 304 128 304 WIRE 256 304 240 304 WIRE 288 304 256 304 WIRE 416 304 416 240 WIRE 416 304 368 304 WIRE 464 304 416 304 WIRE 496 304 464 304 WIRE 128 320 128 304 WIRE 256 320 256 304 WIRE 624 320 624 240 WIRE 624 320 560 320 WIRE 496 336 464 336 WIRE -592 352 -592 336 WIRE -416 352 -416 336 WIRE 464 368 464 336 WIRE 128 400 128 384 WIRE 256 400 256 384 WIRE -176 416 -176 224 WIRE -176 416 -224 416 WIRE 464 464 464 448 WIRE -560 496 -592 496 WIRE -512 496 -560 496 WIRE -416 512 -448 512 WIRE -384 512 -416 512 WIRE -144 512 -224 512 WIRE -16 512 -80 512 WIRE 80 512 80 304 WIRE 80 512 64 512 WIRE -736 528 -736 208 WIRE -512 528 -736 528 WIRE -736 576 -736 528 WIRE -592 576 -592 496 WIRE -304 592 -304 576 WIRE -192 592 -304 592 WIRE -32 592 -32 272 WIRE -32 592 -192 592 WIRE -736 672 -736 656 WIRE -592 672 -592 656 FLAG -416 256 VCC FLAG -304 32 VCC FLAG -384 96 VCC FLAG -304 352 VCC FLAG -384 416 VCC FLAG -416 512 VCO FLAG -416 192 DATA FLAG -192 592 CLR FLAG -416 352 0 FLAG 128 400 0 FLAG 256 400 0 FLAG -592 672 0 FLAG -736 672 0 FLAG -592 352 0 FLAG -688 208 Ramp FLAG -576 176 Dly FLAG -560 496 Ref FLAG -480 224 0 FLAG -480 160 VCC FLAG -480 544 0 FLAG -480 480 VCC FLAG 464 304 Vin FLAG 640 240 VDC FLAG 464 464 0 FLAG 528 352 0 FLAG 528 288 VCC SYMBOL Voltage -416 240 R0 WINDOW 3 28 84 Left 2 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR Value +5V SYMATTR InstName V1 SYMBOL 74hc74 -304 32 R0 WINDOW 40 20 14 Left 2 SYMATTR InstName U1 SYMATTR SpiceLine VCC=5 TRIPDT=1e-9 SYMATTR SpiceLine2 SPEED=1 SYMBOL 74hc74 -304 352 R0 WINDOW 40 -45 260 Left 2 SYMATTR InstName U2 SYMATTR SpiceLine VCC=5 DELAY=0.1 TRIPDT=1e-9 SYMATTR SpiceLine2 SPEED=1 SYMBOL digital\\74hc00 -112 144 R0 WINDOW 40 -42 152 Left 2 SYMATTR InstName U3 SYMATTR SpiceLine VCC=5 TRIPDT=1e-9 SYMATTR SpiceLine2 SPEED=1 SYMBOL res -32 80 M90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName UP SYMATTR Value 1k SYMBOL res 80 496 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName DOWN SYMATTR Value 1k SYMBOL cap 112 320 R0 SYMATTR InstName C1 SYMATTR Value 1n SYMBOL res 256 288 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R3 SYMATTR Value 1k SYMBOL cap 240 320 R0 SYMATTR InstName C2 SYMATTR Value 500p SYMBOL cap 512 224 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName C3 SYMATTR Value 10n SYMBOL cap 608 224 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName C4 SYMATTR Value 1n SYMBOL res 528 144 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R5 SYMATTR Value 1k SYMBOL res 384 288 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R4 SYMATTR Value 1k SYMBOL voltage -592 560 R0 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName V2 SYMATTR Value 2V SYMBOL voltage -736 560 R0 WINDOW 3 4 149 Left 2 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR Value PULSE(0 4 500n 1u 0 0 1u) SYMATTR InstName V3 SYMBOL voltage -592 240 R0 WINDOW 3 -102 146 Left 2 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR Value PULSE(1.8 2.2 0 50u 1ns 1n) SYMATTR InstName V4 SYMBOL opamps\\1pole -480 192 R0 SYMATTR InstName U5 SYMATTR Value2 Avol=1Meg GBW=1e9 Slew=1e9 SYMBOL opamps\\1pole -480 512 R0 SYMATTR InstName U6 SYMATTR Value2 Avol=1Meg GBW=1e9 Slew=1e9 SYMBOL diode -144 112 R270 WINDOW 0 32 32 VTop 2 WINDOW 3 0 32 VBottom 2 SYMATTR InstName X1 SYMATTR Value DN5711 SYMATTR Prefix X SYMBOL diode -80 496 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName X2 SYMATTR Value DN5711 SYMATTR Prefix X SYMBOL Voltage 464 352 R0 WINDOW 3 28 84 Left 2 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR Value 2.5V SYMATTR InstName V5 SYMBOL opamps\\1pole 528 320 R0 WINDOW 123 -119 181 Left 2 SYMATTR InstName U4 SYMATTR Value2 Avol=1Meg GBW=1e6 Slew=1e6 SYMATTR SpiceLine2 en=0 enk=0 in=0 ink=0 Rin=10Meg TEXT -376 -64 Left 2 ;'PFD and Op Amp Analysis TEXT -376 -40 Left 2 !.tran 0 50u 0 TEXT 160 24 Left 2 !.include 74hc.lib TEXT 160 -48 Left 2 !.options plotwinsize=0 TEXT 160 96 Left 2 ;NOTE: Filter values are for illustrative purposes only TEXT 160 -32 Left 2 !.options nomarch TEXT 160 0 Left 2 !.ic V(VDC) = 2.5 TEXT 160 40 Left 2 !.include dn5711.txt TEXT 160 432 Left 2 ;Ripple Filter
In my low voltage custom chips I avoid the OpAmp altogether (VCO control is very high impedance).
Charge pump UP/DN are switchable current mirrors with a defined current (external R) and operate into a series RC to ground (also external, single-pin). Above loop bandwidth this RC is paralleled with another C to "de-spur".
So I get the requisite lead-lag without the pain of an OpAmp struggling to keep up. ...Jim Thompson
--
| James E.Thompson | mens |
| Analog Innovations | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| San Tan Valley, AZ 85142 Skype: Contacts Only | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |
I love to cook with wine. Sometimes I even put it in the food.
I have been following the thread "Boost Converter Efficiency Improvements" and the struggle to improve the analysis speed using the SMS7621.
I tried it in the PFD Analysis circuit and found it was orders of magnitude slower than the 1N5711. I mean really, really slow. It is unusable.
The 1N5711 has an undesirable undershoot when turning off. In real life, the SMS7621 probably has much less undershoot, but it is impossible to use it in LTspice.
Since all we want for that function in the circuit is a fast diode with no undershoot, I looked for another way to perform the same function. It turns out a diode-connected BFG198 is perfect. It is fast and has no undesirable underdshoot when turning off. The model statement is
It obviously doesn't have the same forward drop as a schottky, but if all you need is a fast diode with no undershoot, it works pretty good.
Here is the new PFD Analysis using the BFG198. You can see what a huge difference it makes in the I(UP) and I(DOWN) waveforms. Watch the wrap in the model statement at the end.
Version 4 SHEET 1 4472 800 WIRE 96 32 0 32 WIRE 96 48 96 32 WIRE -176 96 -224 96 WIRE 0 96 0 32 WIRE 0 96 -176 96 WIRE 32 96 0 96 WIRE 96 160 96 144 WIRE -576 176 -592 176 WIRE -512 176 -576 176 WIRE 464 176 448 176 WIRE 560 176 544 176 WIRE -416 192 -448 192 WIRE -384 192 -416 192 WIRE -176 192 -176 96 WIRE -160 192 -176 192 WIRE -688 208 -736 208 WIRE -512 208 -688 208 WIRE -32 208 -48 208 WIRE -160 224 -176 224 WIRE -592 256 -592 176 WIRE 96 256 96 240 WIRE 160 256 96 256 WIRE 448 256 448 176 WIRE 480 256 448 256 WIRE 560 256 560 176 WIRE 560 256 544 256 WIRE 576 256 560 256 WIRE 656 256 640 256 WIRE 672 256 656 256 WIRE 704 256 672 256 WIRE -304 272 -304 256 WIRE -32 272 -32 208 WIRE -32 272 -304 272 WIRE 96 304 96 256 WIRE 160 320 160 256 WIRE 192 320 160 320 WIRE 288 320 272 320 WIRE 320 320 288 320 WIRE 448 320 448 256 WIRE 448 320 400 320 WIRE 496 320 448 320 WIRE 528 320 496 320 WIRE 160 336 160 320 WIRE 288 336 288 320 WIRE 656 336 656 256 WIRE 656 336 592 336 WIRE -592 352 -592 336 WIRE -416 352 -416 336 WIRE 528 352 496 352 WIRE 496 384 496 352 WIRE 96 400 96 384 WIRE 96 400 16 400 WIRE -176 416 -176 224 WIRE -176 416 -224 416 WIRE 16 416 16 400 WIRE 160 416 160 400 WIRE 288 416 288 400 WIRE 96 464 96 400 WIRE 96 464 80 464 WIRE 496 480 496 464 WIRE -560 496 -592 496 WIRE -512 496 -560 496 WIRE -416 512 -448 512 WIRE -384 512 -416 512 WIRE 16 512 -224 512 WIRE -736 528 -736 208 WIRE -512 528 -736 528 WIRE -736 576 -736 528 WIRE -592 576 -592 496 WIRE -304 592 -304 576 WIRE -192 592 -304 592 WIRE -32 592 -32 272 WIRE -32 592 -192 592 WIRE -736 672 -736 656 WIRE -592 672 -592 656 FLAG -416 256 VCC FLAG -304 32 VCC FLAG -384 96 VCC FLAG -304 352 VCC FLAG -384 416 VCC FLAG -416 512 VCO FLAG -416 192 DATA FLAG -192 592 CLR FLAG -416 352 0 FLAG 160 416 0 FLAG 288 416 0 FLAG -592 672 0 FLAG -736 672 0 FLAG -592 352 0 FLAG -688 208 Ramp FLAG -576 176 Dly FLAG -560 496 Ref FLAG -480 224 0 FLAG -480 160 VCC FLAG -480 544 0 FLAG -480 480 VCC FLAG 496 320 Vin FLAG 672 256 VDC FLAG 496 480 0 FLAG 560 368 0 FLAG 560 304 VCC SYMBOL Voltage -416 240 R0 WINDOW 3 28 84 Left 2 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR Value +5V SYMATTR InstName V1 SYMBOL 74hc74 -304 32 R0 WINDOW 40 20 14 Left 2 SYMATTR SpiceLine2 SPEED=1 SYMATTR InstName U1 SYMATTR SpiceLine VCC=5 TRIPDT=1e-9 SYMBOL 74hc74 -304 352 R0 WINDOW 40 -45 260 Left 2 SYMATTR SpiceLine2 SPEED=1 SYMATTR InstName U2 SYMATTR SpiceLine VCC=5 DELAY=0.1 TRIPDT=1e-9 SYMBOL digital\\74hc00 -112 144 R0 WINDOW 40 -42 152 Left 2 SYMATTR SpiceLine2 SPEED=1 SYMATTR InstName U3 SYMATTR SpiceLine VCC=5 TRIPDT=1e-9 SYMBOL res 112 144 M0 SYMATTR InstName UP SYMATTR Value 1k SYMBOL res 112 288 M0 SYMATTR InstName DOWN SYMATTR Value 1k SYMBOL cap 144 336 R0 SYMATTR InstName C1 SYMATTR Value 1n SYMBOL res 288 304 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R3 SYMATTR Value 1k SYMBOL cap 272 336 R0 SYMATTR InstName C2 SYMATTR Value 500p SYMBOL cap 544 240 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName C3 SYMATTR Value 10n SYMBOL cap 640 240 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName C4 SYMATTR Value 1n SYMBOL res 560 160 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R5 SYMATTR Value 1k SYMBOL res 416 304 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R4 SYMATTR Value 1k SYMBOL voltage -592 560 R0 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName V2 SYMATTR Value 2V SYMBOL voltage -736 560 R0 WINDOW 3 4 149 Left 2 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR Value PULSE(0 4 500n 1u 0 0 1u) SYMATTR InstName V3 SYMBOL voltage -592 240 R0 WINDOW 3 -102 146 Left 2 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR Value PULSE(1.8 2.2 0 50u 1ns 1n) SYMATTR InstName V4 SYMBOL opamps\\1pole -480 192 R0 SYMATTR InstName U5 SYMATTR Value2 Avol=1Meg GBW=1e9 Slew=1e9 SYMBOL opamps\\1pole -480 512 R0 SYMATTR InstName U6 SYMATTR Value2 Avol=1Meg GBW=1e9 Slew=1e9 SYMBOL Voltage 496 368 R0 WINDOW 3 28 84 Left 2 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR Value 2.5V SYMATTR InstName V5 SYMBOL opamps\\1pole 560 336 R0 WINDOW 123 -119 181 Left 2 SYMATTR Value2 Avol=1Meg GBW=1e6 Slew=1e6 SYMATTR InstName U4 SYMATTR SpiceLine2 en=0 enk=0 in=0 ink=0 Rin=10Meg SYMBOL Npn 32 48 R0 WINDOW 3 64 76 Left 2 SYMATTR Value BFG198 SYMATTR InstName Q1 SYMBOL Npn 80 416 M0 SYMATTR InstName Q2 SYMATTR Value BFG198 TEXT -376 -64 Left 2 ;'PFD and Op Amp Analysis TEXT -376 -40 Left 2 !.tran 0 50u 0 TEXT 160 24 Left 2 !.include 74hc.lib TEXT 160 -48 Left 2 !.options plotwinsize=0 TEXT 280 120 Left 2 ;NOTE: Filter values are for illustrative purposes only TEXT 160 -32 Left 2 !.options nomarch TEXT 160 0 Left 2 !.ic V(VDC) = 2.5 TEXT 192 448 Left 2 ;Ripple Filter TEXT -488 648 Left 2 !.model BFG198 NPN(IS=1.8998E-15 ISE=7.1424E-14 ISC=
IS = 2.6459E-8 RS = 12.5 N = 1.01 TT = 1E-11 CJO = 0.13pF M = 0.35 EG = 0.69 XTI = 2 FC = 0.5 BV = 3 IBV = 1E-5 VJ = 0.51
...Jim Thompson
--
| James E.Thompson | mens |
| Analog Innovations | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| San Tan Valley, AZ 85142 Skype: Contacts Only | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |
I love to cook with wine. Sometimes I even put it in the food.
Nonsense. That's no more parameters than typically in a BJT.
Simplistic will zing you in the ass every time.
And then you whined when a simulation was taking forever in LTspice?? ...Jim Thompson
--
| James E.Thompson | mens |
| Analog Innovations | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| San Tan Valley, AZ 85142 Skype: Contacts Only | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |
I love to cook with wine. Sometimes I even put it in the food.
That does not follow. It's the standard Gummell-Poon model, with the same n umber of parameters as any other transistor.
It is an 8GHz device, and that could slow down your simulation by imposing a small step size, but it's not the number of parameters involved that woul d create that problem, but their values. Since it is being used as a diode, this probably wouldn't be a issue.
It turns out just adding a diode without selecting any model seems to work fine. That is a lot easier than playing with a BFG198. It doesn't matter what is performing that function, as long as it doesn't undershoot at turnoff like the 1N5711. That messes up the waveforms and makes it harder to understand what is going on.
The purpose for the analysis is to show how the PFD and op amp work. It clearly shows that increasing the NAND delay has little or no effect on the op amp input as you claimed.
You did a Bode plot of the op amp with feedback. That is trivial. You cannot do a Bode plot of the entire loop with the PFD using AC Analysis.
You described the phase detector verbally and the changes you had to make. The PFD I posted is the standard Dual-D with NAND feedback. It should operate exactly the same as yours, if it is a standard frequency/phase detector.
You posted the op amp and feedback components.
The PFD analysis I posted is exactly the same configuration. Op amp + goes to a reference voltage. Loop filter goes to op amp -.
The UP and DOWN logic levels go through diode and series resistor to op amp -.
Exactly the same configuration, except you have no ripple filter at the input of the op amp.
Moron. If a part model slows a sim to the point of unusability, it needs to be changed. Or give up simulating it.
Idiot. In a basic circuit like the phase detector amp that I posted, and in many other situations, like the boost converter soft-start I posted, what you're after is modeling loop dynamics. A simple diode model, or an ideal diode model, can work fine *IF* you understand what's going on. Nobody sane is going to model every parasitic of every part.
A simulation that takes a day, or a week, per run isn't useful in iterating loop dynamics. If the loop is linear enough, like our FPGA PLL, it then makes sense to use 10 minutes of classic Bode analysis. Or if it's too nonlinear, like my boost converter, breadboard.
The third choice, the one I generally use, is to just design the board the way that ought to work, lay it out as rev A, and let manufacturing build one. Leave in enough hooks to get out of trouble. IC designers can't do that, which distorts your perspective. The other thing that distorts your perspective is that you're a mean-spirited, paranoid, vain old git.
On a board with 800 parts, 11 power supplies, ARM CPU, a couple of FPGAs, thermal issues, transmission lines, 8-layer PCB to lay out and check, all sorts of stuff, we can't spend weeks simulating every subcircuit. Most of our stuff works rev A, first time, with little or no simulation. If we have to tweak a couple of parts values, no big deal: we save tons of time by working this way.
For example: we use a lot of resistor and capacitor networks to save space and production costs, but they lock you into fixed ratios. At design reviews, one thing we do is look for places to use networks, and places where networks could create hazards.
Have I mentioned lately that you're an idiot?
--
John Larkin Highland Technology Inc
www.highlandtechnology.com jlarkin at highlandtechnology dot com
Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators
Custom timing and laser controllers
Photonics and fiberoptic TTL data links
VME analog, thermocouple, LVDT, synchro, tachometer
Multichannel arbitrary waveform generators
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