8051F020 series, 5V tolerant input schematic?

from the datasheet the old Virtex fpgas had a "zener like structure to ground" for 5V pci compliance I just looked at a STM32 to see if there was anything about the 5V tolerance in the datasheet

it doesn't say how but it allows Vdd+4V input on 5V tolerant pins, max +0/-5mA injected

normal IO is 4V and +5/-5mA

-Lasse

According to Xilinx, 5V tolerant pins can add a dozen or so components per pin. Probably, as Lasse says, it behaves something like a zener for inputs.

If it's programmable as an output too, they have to add some parts to keep current from flowing back through the off p-channel.

I don't think you'll find real schematics openly available for this stuff- on-chip ESD protection seems to be kind of a trade secret.

That would be ok but they should state a max peak current. Yet nothing is stated.

They are only input-tolerant, they can't output 5V.

Yeah, that was only available in the good old days. "Modern" datasheets leave a lot to be desired when it comes to hardware details.

"5V-tolerant" pins function by disconnect, not by clamping (somewhat like the schemes used in hi-Z when unpowered bus devices). The voltage limit is determined by oxide breakdown. ...Jim Thompson

Because no current flows. See my related post.

...Jim Thompson

I guess they assume you'll never exceed the absolute maximum voltage limits of +5.8/-0.3, so no significant current will ever flow.

So you mean like a linear regulator? Because a hard disconnect would cause the uC to read this pin wrongly, and it reads it correctly. Or do you mean it disconnects somewhere above 5V?

If they say 5.8V, what's you gut feel it could really take if a surge or pulse salvo of a few msec comes through? It's amplitude would be slightly over 7V. because it leans into protective diodes we have up front of the uC port. Those are regular Si-diodes against the 5V rail and GND.

Ok, but in real life that's almost unprotectable. The way I usually do it, there is a diode against the 5V rail, followed by a resistor, then the port pin. If the pulse from hell comes along that diode can briefly lean in so badly that Vf goes slightly above 2V, meaning over 7V total. Bigger diodes aren't an option because that messes up the signal, on account of their large capacitance.

5V-tolerant OUTPUTS, that is outputs which also serve as INPUTS (bi-directional bus I/O, etc.) use a disconnect above local VDD. Visualize the dual series device with "body" at midpoint, that I've shown here before as a battery-charge control device.

As in...

DC over-voltage is a no-no... ESD only. ...Jim Thompson

You're still fixated on clamping, which would make no sense whatsoever in a mixed signal low power digital environment. The high voltage tolerant inputs are a variation of the theme shown below in one form or another. Operation is self-explanatory: Please view in a fixed-width font such as Courier.

. . . . EX High Voltage Tolerant Input . . . . VDD . | PMOS keeper . - . || . ||o----------. . VDD _|| | . | | | . | G | | . input ___ | | \ | | \ pad . pad ___ | | \ | | \ to core . _ D | | S | | \ | | \ _ . |_| ------ ----+-----| o --+---| o----|_| . | / | / . series | / | / buffer . NMOS | / Schmitt | / CMOS . .

It's all I/O, since it's a 8051-family uC with regular cofigurable ports.

That would work, provided the comparator is past, has little or no hysteresis and the FETs are snappy. Because the signal integrity of an incoming 5V data stream must be maintained to full spec'd speed.

DC will never exceed 5V and abs max is 5.8V. So you think ESD or surges (the usual machine-gun style bursts in EMC tests) are ok? We have it clamped to a 5V rail but it could really lean into those clamp diodes.

This thread rattles around avoiding specifics. Is the "5V-tolerant" input an input that has 3.3V as VDD? ...Jim Thompson

mixed signal low power digital environment. The high voltage tolerant inputs are a variation of the theme shown below in one form or another. Operation is self-explanatory:

That looks vaguely like my USB patent on the work I did for Intel. I'll dredge that up and post it. ...Jim Thompson

surges

Yes, the SiLabs C8051F020 type part nominally uses a 3.3V supply for the I/O Rail VDD. These pins default to typical 8051 style with quasi- bidirectional behavior with onboard pullup circuitry. The port pins can also be programmed to be output driven by a totem pole output to the VDD rail.

I'd (thankfully) almost forgotten about those miserable quasi bi-directional port pins.

The schematic on page 161 does not appear to show the brief hard (~100:1) pullup on 0->1 port-pin transition that old-skule 80C51s have. If it's present it would be back of the ESD circuitry anyway.

Yes, it is, that's what I wrote in the original post :-)

The uC has only a 3.3V supply, no 5V supply. But some lines coming in are from logic that is on 5V, so can't be ESD-clamped lower than 5V.

The problem is that, as usual, they write nothing about what's in the Schmitt buffer at the bottom of that schematic. Sometimes I wish IC designers were closer to the board level world and thus release more of the info that we really need. Because we board level guys have to deal with ESD pulses, RF bursts, nearby lightning, and whatnot. And then like in this case we have to get the whole thing through myriad agency certs which require good rationale and math.

It's management. Note how LTspice is going all encrypted?

And Analog Devices modeling efforts are now managed by a MARKETING VP, and they are ultimately heading to requiring simulation of their parts ONLY on their web-based simulator. ...Jim Thompson

dumping

is

OK. A "5V-tolerant" input accepts 5V signals because it has no ESD diode to VDD. ESD events are handled by what is called a "snap diode" to ground which avalanches at higher voltages. ...Jim Thompson