I have made an output device that attaches to older 8 bit computers. The MSB of the address bus goes though some gates and the select clocks a 74273 d type flipflop. The LSB goes into the inputs of the
273. It works great as ttl chips. I've installed the xilinx webpack and am using the schematic entry and it looks very simple to implement. I'm using the FD flipflop since I don't use the clear. Unfortunately it doesn't work. I've run the clock to an output pin and connected a 74hct273 in parallel to verify everything else and the ttl chip works correctly every time. The output of the 9536 seems to be more of a random number generator.The modelsim looks like what I would expect. Is it possible the clock on the flip flop is occuring before all the address pins get settled? I'm new to CPLDs am I missing something obvious?
I've played with this for a couple of days now. One interesting thing I did find. I inserted a nand gate in the clock line followed by an inverter. I branched the ouput of the nand back around into the other input of the nand. I assume this would cause the clock signal to oscillate while the decoders selected the flip flop. What's interesting is this causes the flip flop to clock all 8 bits correctly better than half the time. I'm sure that would tell me something if I knew what I was doing. :)
Any help would be appreciated, thanks.