Microchip PIC32 datasheet: 20.0 Parallel master port (PMP)

20.0 PARALLEL MASTER PORT (PMP)

Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 13. “Parallel Master Port (PMP)” (DS61128) of the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).

2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information.

The PMP is a parallel 8-bit/16-bit input/output module specifically designed to communicate with a wide variety of parallel devices, such as communications peripherals, LCDs, external memory devices and microcontrollers. Because the interface to parallel peripherals varies significantly, the PMP module is highly configurable.

Key features of the PMP module include:

• 8-bit,16-bit interface
• Up to 16 programmable address lines
• Up to two Chip Select lines
• Programmable strobe options
  • Individual read and write strobes, or
  • Read/write strobe with enable strobe
• Address auto-increment/auto-decrement
• Programmable address/data multiplexing
• Programmable polarity on control signals
• Parallel Slave Port support
  • Legacy addressable
  • Address support
  • 4-byte deep auto-incrementing buffer
• Programmable Wait states
• Operate during CPU Sleep and Idle modes
• Fast bit manipulation using CLR, SET and INV registers
• Freeze option for in-circuit debugging

Note: On 64-pin devices, data pins PMD<15:8> are not available.

FIGURE 20-1: PMP MODULE PINOUT AND CONNECTIONS TO EXTERNAL DEVICES

Note 1: On 64-pin devices, data pins PMD<15:8> are not available in 16-bit Master modes.

NOTES:

21.0 REAL-TIME CLOCK AND CALENDAR (RTCC)

Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 29. “Real-Time Clock and Calendar (RTCC)” (DS61125) of the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).

2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information.

The PIC32MX RTCC module is intended for applications in which accurate time must be maintained for extended periods of time with minimal or no CPU intervention. Low-power optimization provides extended battery lifetime while keeping track of time.

The following are some of the key features of this module:

• Time: Hours, Minutes and Seconds
• 24-Hour Format (Military Time)
• Visibility of One-Half-Second Period
• Provides Calendar: Weekday, Date, Month and Year
• Alarm Intervals are configurable for Half of a Second, One Second, 10 Seconds, One Minute, 10 Minutes, One Hour, One Day, One Week, One Month and One Year
• Alarm Repeat with Decrementing Counter
• Alarm with Indefinite Repeat: Chime
• Year Range: 2000 to 2099
• Leap Year Correction
• BCD Format for Smaller Firmware Overhead
• Optimized for Long-Term Battery Operation
• Fractional Second Synchronization
• User Calibration of the Clock Crystal Frequency with Auto-Adjust
• Calibration Range: ±0.66 Seconds Error per Month
• Calibrates up to 260 ppm of Crystal Error
• Requirements: External 32.768 kHz Clock Crystal
• Alarm Pulse or Seconds Clock Output on RTCC pin

FIGURE 21-1: RTCC BLOCK DIAGRAM

NOTES:

22.0 10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC)

Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. Refer to Section 17. “10-bit Analog-to-Digital Converter (ADC)” (DS61104) of the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).

2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information.

The PIC32MX3XX/4XX 10-bit Analog-to-Digital Converter (ADC) includes the following features:

• Successive Approximation Register (SAR) conversion
• Up to 1000 kilo samples per second (ksps) conversion speed
• Up to 16 analog input pins
• External voltage reference input pins
• One unipolar, differential Sample-and-Hold Amplifier (SHA)
• Automatic Channel Scan mode
• Selectable conversion trigger source
• 16-word conversion result buffer
• Selectable Buffer Fill modes
• Eight conversion result format options
• Operation during CPU Sleep and Idle modes

A block diagram of the 10-bit ADC is illustrated in Figure 22-1. The 10-bit ADC has 16 analog input pins, designated AN0-AN15. In addition, there are two analog input pins for external voltage reference connections. These voltage reference inputs may be shared with other analog input pins and may be common to other analog module references.

The analog inputs are connected through two multiplexers (MUXs) to one SHA. The analog input MUXs can be switched between two sets of analog inputs between conversions. Unipolar differential conversions are possible on all channels, other than the pin used as the reference, using a reference input pin (see Figure 22-1).

The Analog Input Scan mode sequentially converts user-specified channels. A control register specifies which analog input channels will be included in the scanning sequence.

The 10-bit ADC is connected to a 16-word result buffer. Each 10-bit result is converted to one of eight, 32-bit output formats when it is read from the result buffer.

FIGURE 22-1: ADC1 MODULE BLOCK DIAGRAM

Note 1: VREF+, VREF- inputs can be multiplexed with other analog inputs.

FIGURE 22-2: ADC CONVERSION CLOCK PERIOD BLOCK DIAGRAM

23.0 COMPARATOR

Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. Refer to Section 19. “Comparator” (DS61110) of the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).

2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information.

The PIC32MX3XX/4XX Analog Comparator module contains one or more comparator(s) that can be configured in a variety of ways.

Following are some of the key features of this module:

• Selectable inputs available include:
  • Analog inputs multiplexed with I/O pins
  • On-chip internal absolute voltage reference (IVREF)
  • Comparator voltage reference (CVREF)
• Outputs can be inverted
• Selectable interrupt generation

A block diagram of the comparator module is illustrated in Figure 23-1.

FIGURE 23-1: COMPARATOR BLOCK DIAGRAM

Note 1: On USB variants, when USB is enabled, this pin is controlled by the USB module and therefore is not available as a comparator input. 2: Internally connected.

NOTES:

24.0 COMPARATOR VOLTAGE REFERENCE (CVREF)

Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. Refer to Section 20. “Comparator Voltage Reference (CVREF)” (DS61109) of the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).

2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information.

The CVREF is a 16-tap, resistor ladder network that provides a selectable reference voltage. Although its primary purpose is to provide a reference for the analog comparators, it also may be used independently of them.

A block diagram of the module is illustrated in Figure 24-1. The resistor ladder is segmented to provide two ranges of voltage reference values and has a power-down function to conserve power when the reference is not being used. The module’s supply reference can be provided from either device VDD/VSS or an external voltage reference. The CVREF output is available for the comparators and typically available for pin output.

The comparator voltage reference has the following features:

• High and low range selection
• Sixteen output levels available for each range
• Internally connected to comparators to conserve device pins
• Output can be connected to a pin

FIGURE 24-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM

NOTES:

DS61143H-page 128 © 2011 Microchip Technology Inc.

25.0 POWER-SAVING FEATURES

Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 10. “Power-Saving Features” (DS61130) of the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).

2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information.

This section describes power-saving for the PIC32MX3XX/4XX. The PIC32MX devices offer a total of nine methods and modes that are organized into two categories that allow the user to balance power consumption with device performance. In all of the methods and modes described in this section, power-saving is controlled by software.

25.1 Power-Saving with CPU Running

When the CPU is running, power consumption can be controlled by reducing the CPU clock frequency, lowering the PBCLK, and by individually disabling modules. These methods are grouped into the following modes:

• FRC Run mode: the CPU is clocked from the FRC clock source with or without postscalers.
• LPRC Run mode: the CPU is clocked from the LPRC clock source.
• Sosc Run mode: the CPU is clocked from the Sosc clock source.
• Peripheral Bus Scaling mode: peripherals are clocked at programmable fraction of the CPU clock (SYSCLK).

25.2 CPU Halted Methods

The device supports two power-saving modes, Sleep and Idle, both of which halt the clock to the CPU. These modes operate with all clock sources, as listed below:

• Posc Idle Mode: the system clock is derived from the Posc. The system clock source continues to operate. Peripherals continue to operate, but can optionally be individually disabled.
• FRC Idle Mode: the system clock is derived from the FRC with or without postscalers. Peripherals continue to operate, but can optionally be individually disabled.
• Sosc Idle Mode: the system clock is derived from the Sosc. Peripherals continue to operate, but can optionally be individually disabled.
• LPRC Idle Mode: the system clock is derived from the LPRC. Peripherals continue to operate, but can optionally be individually disabled. This is the lowest power mode for the device with a clock running.
• Sleep Mode: the CPU, the system clock source, and any peripherals that operate from the system clock source, are halted. Some peripherals can operate in Sleep using specific clock sources. This is the lowest power mode for the device.

25.3 Power-Saving Operation

The purpose of all power-saving is to reduce power consumption by reducing the device clock frequency. To achieve this, low-frequency clock sources can be selected. In addition, the peripherals and CPU can be halted or disabled to further reduce power consumption.

25.3.1 SLEEP MODE

Sleep mode has the lowest power consumption of the device Power-Saving operating modes. The CPU and most peripherals are halted. Select peripherals can continue to operate in Sleep mode and can be used to wake the device from Sleep. See the individual peripheral module sections for descriptions of behavior in Sleep mode.

Sleep mode includes the following characteristics:

• The CPU is halted.
• The system clock source is typically shut down. See Section 25.3.2 “Idle Mode” for specific information.
• There can be a wake-up delay based on the oscillator selection.
• The Fail-Safe Clock Monitor (FSCM) does not operate during Sleep mode.
• The BOR circuit, if enabled, remains operative during Sleep mode.
• The WDT, if enabled, is not automatically cleared prior to entering Sleep mode.
• Some peripherals can continue to operate in Sleep mode. These peripherals include I/O pins that detect a change in the input signal, WDT, ADC, UART and peripherals that use an external clock input or the internal LPRC oscillator, e.g., RTCC and Timer 1.
• I/O pins continue to sink or source current in the same manner as they do when the device is not in Sleep.
• The USB module can override the disabling of the Posc or FRC. Refer to Section 11.0 “USB On-The-Go (OTG)” for specific details.
• Some modules can be individually disabled by software prior to entering Sleep in order to further reduce consumption.

The processor will exit, or ‘wake-up’, from Sleep on one of the following events:

• On any interrupt from an enabled source that is operating in Sleep. The interrupt priority must be greater than the current CPU priority.
• On any form of device Reset.
• On a WDT time-out. See Section 26.2 “Watchdog Timer (WDT)”.

If the interrupt priority is lower than or equal to current priority, the CPU will remain halted, but the PBCLK will start running and the device will enter into Idle mode.

Note: There is no FRZ mode for this module.

25.3.2 IDLE MODE

In the Idle mode, the CPU is halted but the System clock (SYSCLK) source is still enabled. This allows peripherals to continue operation when the CPU is halted. Peripherals can be individually configured to halt when entering Idle by setting their respective SIDL bit. Latency when exiting Idle mode is very low due to the CPU oscillator source remaining active.

Note: Changing the PBCLK divider ratio requires recalculation of peripheral timing. For example, assume the UART is configured for 9600 baud with a PB clock ratio of 1:1 and a Posc of 8 MHz. When the PB clock divisor of 1:2 is used, the input frequency to the baud clock is cut in half; therefore, the baud rate is reduced to 1/2 its former value. Due to numeric truncation in calculations (such as the baud rate divisor), the actual baud rate may be a tiny percentage different than expected. For this reason, any timing calculation required for a peripheral should be performed with the new PB clock frequency instead of scaling the previous value based on a change in PB divisor ratio.

Oscillator start-up and PLL lock delays are applied when switching to a clock source that was disabled and that uses a crystal and/or the PLL. For example, assume the clock source is switched from Posc to LPRC just prior to entering Sleep in order to save power. No oscillator start-up delay would be applied when exiting Idle. However, when switching back to Posc, the appropriate PLL and/or oscillator startup/lock delays would be applied.

The device enters Idle mode when the SLPEN (OSCCON<4>) bit is clear and a WAIT instruction is executed.

The processor will wake or exit from Idle mode on the following events:

• On any interrupt event for which the interrupt source is enabled. The priority of the interrupt event must be greater than the current priority of CPU. If the priority of the interrupt event is lower than or equal to current priority of CPU, the CPU will remain halted and the device will remain in Idle mode.
• On any source of device Reset.
• On a WDT time-out interrupt. See Section 26.2 “Watchdog Timer (WDT)”.

25.3.3 PERIPHERAL BUS SCALING METHOD

Most of the peripherals on the device are clocked using the PBCLK. The peripheral bus can be scaled relative to the SYSCLK to minimize the dynamic power consumed by the peripherals. The PBCLK divisor is controlled by PBDIV<1:0> (OSCCON<20:19>), allowing SYSCLK-to-PBCLK ratios of 1:1, 1:2, 1:4 and 1:8. All peripherals using PBCLK are affected when the divisor is changed. Peripherals such as USB, Interrupt Controller, DMA, Bus Matrix and Prefetch Cache are clocked directly from SYSCLK, as a result, they are not affected by PBCLK divisor changes

Changing the PBCLK divisor affects:

• The CPU to peripheral access latency. The CPU has to wait for next PBCLK edge for a read to complete. In 1:8 mode this results in a latency of one to seven SYSCLKs.
• The power consumption of the peripherals. Power consumption is directly proportional to the frequency at which the peripherals are clocked. The greater the divisor, the lower the power consumed by the peripherals.

To minimize dynamic power the PB divisor should be chosen to run the peripherals at the lowest frequency that provides acceptable system performance. When selecting a PBCLK divider, peripheral clock requirements such as baud rate accuracy should be taken into account. For example, the UART peripheral may not be able to achieve all baud rate values at some PBCLK divider depending on the SYSCLK value.

26.0 SPECIAL FEATURES

Note: This data sheet summarizes the features of the PIC32MX3XX/4XX family family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 9. “Watchdog Timer and Power-up Timer” (DS61114), Section 32. “Configuration” (DS61124) and Section 33. “Programming and Diagnostics” (DS61129) of the PIC32 Family Reference Manual, which is available from the Microchip web site (www.microchip.com/PIC32).

PIC32MX3XX/4XX devices include several features intended to maximize application flexibility and reliability and minimize cost through elimination of external components. These are:

• Flexible Device Configuration
• Watchdog Timer
• JTAG Interface
• In-Circuit Serial Programming™ (ICSP™)

26.1 Configuration Bits

The Configuration bits can be programmed to select various device configurations.

REGISTER 26-1: DEVCFG0: DEVICE CONFIGURATION WORD 0

\begin{tabular}{|l|c|c|c|c|c|c|c|c|} \hline Bit & Bit & Bit & Bit & Bit & Bit & Bit & Bit & Bit \ Range & 31/23/15/7 & 30/22/14/6 & 29/21/13/5 & 28/20/12/4 & 27/19/11/3 & 26/18/10/2 & 25/17/9/1 & 24/16/8/0 \ \hline \multirow{2}{}{31:24} & r-0 & r-1 & r-1 & R/P & r-1 & r-1 & r-1 & R/P \ \cline{2-9} & --- & --- & --- & CP & --- & --- & --- & BWP \ \hline \multirow{2}{}{23:16} & r-1 & r-1 & r-1 & r-1 & R/P & R/P & R/P & R/P \ \cline{2-9} & --- & --- & --- & --- & \multicolumn{4}{c|}{PWP<7:4>} \ \hline \multirow{2}{}{15:8} & R/P & R/P & R/P & R/P & r-1 & r-1 & r-1 & r-1 \ \cline{2-9} & \multicolumn{4}{c|}{PWP<3:0>} & --- & --- & --- & --- \ \hline \multirow{2}{}{7:0} & r-1 & r-1 & r-1 & r-1 & R/P & r-1 & R/P & R/P \ \cline{2-9} & --- & --- & --- & --- & ICESEL & --- & \multicolumn{2}{c|}{DEBUG<1:0>} \ \hline \end{tabular}

Legend: R = Readable bit U = Unimplemented bit W = Writable bit -n = Bit Value at POR: ('0', '1', x = Unknown) P = Programmable bit r = Reserved bit

bit 31 Reserved: Write ‘0’ bit 30-29 Reserved: Write ‘1’ bit 28 CP: Code-Protect bit Prevents boot and program Flash memory from being read or modified by an external programming device. 1 = Protection disabled 0 = Protection enabled bit 27-25 Reserved: Write ‘1’ bit 24 BWP: Boot Flash Write-Protect bit Prevents boot Flash memory from being modified during code execution. 1 = Boot Flash is writable 0 = Boot Flash is not writable bit 23-20 Reserved: Write ‘1’

REGISTER 26-1: DEVCFG0: DEVICE CONFIGURATION WORD 0 (CONTINUED)

bit 19-12 PWP<7:0>: Program Flash Write-Protect bits

Prevents selected program Flash memory pages from being modified during code execution. The PWP bits represent the one’s compliment of the number of write protected program Flash memory pages.

• 1111111 = Disabled
• 11111110 = 0xBD00_0FFF
• 11111101 = 0xBD00_1FFF
• 11111100 = 0xBD00_2FFF
• 11111011 = 0xBD00_3FFF
• 11111010 = 0xBD00_4FFF
• 11111001 = 0xBD00_5FFF
• 11111000 = 0xBD00_6FFF
• 11110111 = 0xBD00_7FFF
• 11110110 = 0xBD00_8FFF
• 11110101 = 0xBD00_9FFF
• 11110100 = 0xBD00_AFFF
• 11110011 = 0xBD00_BFFF
• 11110010 = 0xBD00_CFFF
• 11110001 = 0xBD00_DFFF
• 11110000 = 0xBD00_EFFF
• 11101111 = 0xBD00_FFFF
• .
• .
• .
• 01111111 = 0xBD07_FFFF

bit 11-4 Reserved: Write ‘1’

bit 3 ICESSEL: In-Circuit Emulator/Debugger Communication Channel Select bit

• 1 = PGEC2/PGED2 pair is used
• 0 = PGEC1/PGED1 pair is used

bit 2 Reserved: Write ‘1’

bit 1-0 DEBUG<1:0>: Background Debugger Enable bits (forced to ‘11’ if code-protect is enabled)

• 11 = Debugger disabled
• 10 = Debugger enabled
• 01 = Reserved (same as ‘11’ setting)
• 00 = Reserved (same as ‘11’ setting)

REGISTER 26-2: DEVCFG1: DEVICE CONFIGURATION WORD 1

Legend:

R = Readable bit
W = Writable bit
P = Programmable bit
r = Reserved bit
U = Unimplemented bit
-n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)

bit 31-24 Reserved: Write ‘1’

bit 23 FWD TEN: Watchdog Timer Enable bit
1 = The WDT is enabled and cannot be disabled by software
0 = The WDT is not enabled; it can be enabled in software

bit 22-21 Reserved: Write ‘1’

bit 20-16 WDT PS<4:0>: Watchdog Timer Postscale Select bits
10100 = 1:1048576
10011 = 1:524288
10010 = 1:262144
10001 = 1:131072
10000 = 1:65536
01111 = 1:32768
01110 = 1:16384
01101 = 1:8192
01100 = 1:4096
01011 = 1:2048
01010 = 1:1024
01001 = 1:512
01000 = 1:256
00111 = 1:128
00110 = 1:64
00101 = 1:32
00100 = 1:16
00011 = 1:8
00010 = 1:4
00001 = 1:2
00000 = 1:1
All other combinations not shown result in operation = ‘10100’

bit 15-14 FCKSM<1:0>: Clock Switching and Monitor Selection Configuration bits
1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled
01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled
00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled

Note 1: Do not disable Posc (POSCMOD = 00) when using this oscillator source.

REGISTER 26-2: DEVCFG1: DEVICE CONFIGURATION WORD 1 (CONTINUED)

bit 13-12 FPBDIV<1:0>: Peripheral Bus Clock Divisor Default Value bits 11 = PBCLK is SYSCLK divided by 8 10 = PBCLK is SYSCLK divided by 4 01 = PBCLK is SYSCLK divided by 2 00 = PBCLK is SYSCLK divided by 1

bit 11 Reserved: Write '1'

bit 10 OSCIOFNC: CLKO Enable Configuration bit 1 = CLKO output signal active on the OSCO pin; primary oscillator must be disabled or configured for the External Clock mode (EC) for the CLKO to be active (POSCMOD<1:0> = 11 OR 00) 0 = CLKO output disabled

bit 9-8 POSCMOD<1:0>: Primary Oscillator Configuration bits 11 = Primary oscillator disabled 10 = HS oscillator mode selected 01 = XT oscillator mode selected 00 = External clock mode selected

bit 7 IESO: Internal External Switchover bit 1 = Internal External Switchover mode enabled (Two-Speed Start-up enabled) 0 = Internal External Switchover mode disabled (Two-Speed Start-up disabled)

bit 6 Reserved: Write '1'

bit 5 FSOSCEN: Secondary Oscillator Enable bit 1 = Enable Secondary Oscillator 0 = Disable Secondary Oscillator

bit 4-3 Reserved: Write '1'

bit 2-0 FNOSC<2:0>: Oscillator Selection bits 111 = Fast RC Oscillator with divide-by-N (FRCDIV) 110 = FRCDIV16 Fast RC Oscillator with fixed divide-by-16 postscaler 101 = Low-Power RC Oscillator (LPRC) 100 = Secondary Oscillator (Sosc) 011 = Primary Oscillator with PLL module (XT+PLL, HS+PLL, EC+PLL) 010 = Primary Oscillator (XT, HS, EC)(1) 001 = Fast RC Oscillator with divide-by-N with PLL module (FRCDIV+PLL) 000 = Fast RC Oscillator (FRC)

Note 1: Do not disable Posc (POSCMOD = 00) when using this oscillator source.

DS61143H-page 134 © 2011 Microchip Technology Inc.

REGISTER 26-3: DEVCFG2: DEVICE CONFIGURATION WORD 2

Legend:

R = Readable bit
W = Writable bit
P = Programmable bit
r = Reserved bit
U = Unimplemented bit
-n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)

bit 31-19 Reserved: Write ‘1’

bit 18-16 FPLLODIV<2:0>: Default Postscaler for PLL bits
111 = PLL output divided by 256
110 = PLL output divided by 64
101 = PLL output divided by 32
100 = PLL output divided by 16
011 = PLL output divided by 8
010 = PLL output divided by 4
001 = PLL output divided by 2
000 = PLL output divided by 1

bit 15 UPLLEN: USB PLL Enable bit
1 = Disable and bypass USB PLL
0 = Enable USB PLL

bit 14-11 Reserved: Write ‘1’

bit 10-8 UPLLIDIV<2:0>: PLL Input Divider bits
111 = 12x divider
110 = 10x divider
101 = 6x divider
100 = 5x divider
011 = 4x divider
010 = 3x divider
010 = 3x divider
001 = 2x divider
000 = 1x divider

bit 7 Reserved: Write ‘1’

bit 6-4 FPLLMUL<2:0>: PLL Multiplier bits
111 = 24x multiplier
110 = 21x multiplier
101 = 20x multiplier
100 = 19x multiplier
011 = 18x multiplier
010 = 17x multiplier
001 = 16x multiplier
000 = 15x multiplier

bit 3 Reserved: Write ‘1’

bit 2-0 FPLLIDIV<2:0>: PLL Input Divider bits
111 = 12x divider
110 = 10x divider
101 = 6x divider
100 = 5x divider
011 = 4x divider
010 = 3x divider
001 = 2x divider
000 = 1x divider

REGISTER 26-4: DEVCFG3: DEVICE CONFIGURATION WORD 3

Legend: R = Readable bit W = Writable bit P = Programmable bit r = Reserved bit U = Unimplemented bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)

bit 31-16 Reserved: Write ‘1’ bit 15-0 USERID<15:0>: This is a 16-bit value that is user defined and is readable via ICSP™ and JTAG

REGISTER 26-5: DEVID: DEVICE AND REVISION ID REGISTER

Legend: R = Readable bit W = Writable bit P = Programmable bit r = Reserved bit U = Unimplemented bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)

bit 31-28 VER<3:0>: Revision Identifier bits(1) bit 27-0 DEVID<27:0>: Device ID(1)

Note 1: See the “PIC32MX Flash Programming Specification” (DS61145) for a list of Revision and Device ID values.

26.2 Watchdog Timer (WDT)

This section describes the operation of the WDT and Power-Up Timer of the PIC32MX3XX/4XX.

The WDT, when enabled, operates from the internal Low-Power Oscillator (LPRC) clock source and can be used to detect system software malfunctions by resetting the device if the WDT is not cleared periodically in software. Various WDT time-out periods can be selected using the WDT postscaler. The WDT can also be used to wake the device from Sleep or Idle mode.

The following are some of the key features of the WDT module:

• Configuration or software controlled • User-configurable time-out period • Can wake the device from Sleep or Idle

FIGURE 26-1: WATCHDOG AND POWER-UP TIMER BLOCK DIAGRAM

26.3 On-Chip Voltage Regulator

All PIC32MX3XX/4XX device’s core and digital logic are designed to operate at a nominal 1.8V. To simplify system designs, most devices in the PIC32MX3XX/4XX incorporate an on-chip regulator providing the required core logic voltage from VDD.

The internal 1.8V regulator is controlled by the ENVREG pin. Tying this pin to VDD enables the regulator, which in turn provides power to the core. A low ESR capacitor (such as tantalum) must be connected to the VCORE/VCAP pin (Figure 26-2). This helps to maintain the stability of the regulator. The recommended value for the filer capacitor is provided in Section 29.1 “DC Characteristics”.

Note: It is important that the low ESR capacitor is placed as close as possible to the VCORE/VCAP pin.

Tying the ENVREG pin to VSS disables the regulator. In this case, separate power for the core logic at a nominal 1.8V must be supplied to the device on the VCORE/VCAP pin.

Alternatively, the VCORE/VCAP and VDD pins can be tied together to operate at a lower nominal voltage. Refer to Figure 26-2 for possible configurations.

26.3.1 ON-CHIP REGULATOR AND POR

When the voltage regulator is enabled, it takes fixed delay for it to generate output. During this time, designated as TPU, code execution is disabled. TPU is applied every time the device resumes operation after any power-down, including Sleep mode.

If the regulator is disabled, a separate Power-up Timer (PWRT) is automatically enabled. The PWRT adds a fixed delay of TPWRT at device start-up. See Section 29.0 “Electrical Characteristics” for more information on TPU AND TPWRT.

26.3.2 ON-CHIP REGULATOR AND BOR

When the on-chip regulator is enabled, PIC32MX3XX/4XX devices also have a simple brown-out capability. If the voltage supplied to the regulator is inadequate to maintain a regulated level, the regulator Reset circuitry will generate a Brown-out Reset. This event is captured by the BOR flag bit (RCON<1>). The brown-out voltage levels are specific in Section 29.1 “DC Characteristics”.

26.3.3 POWER-UP REQUIREMENTS

The on-chip regulator is designed to meet the power-up requirements for the device. If the application does not use the regulator, then strict power-up conditions must be adhered to. While powering up, VCORE must never exceed VDD by 0.3 volts.

FIGURE 26-2: CONNECTIONS FOR THE ON-CHIP REGULATOR

Note 1: These are typical operating voltages. Refer to Section 29.1 “DC Characteristics” for the full operating ranges of VDD and VCORE.

26.4 Programming and Diagnostics

PIC32MX3XX/4XX devices provide a complete range of programming and diagnostic features that can increase the flexibility of any application using them. These features allow system designers to include:

• Simplified field programmability using two-wire In-Circuit Serial Programming™ (ICSP™) interfaces
• Debugging using ICSP
• Programming and debugging capabilities using the EJTAG extension of JTAG
• JTAG boundary scan testing for device and board diagnostics

PIC32MX devices incorporate two programming and diagnostic modules, and a trace controller, that provide a range of functions to the application developer.

FIGURE 26-3: BLOCK DIAGRAM OF PROGRAMMING, DEBUGGING AND TRACE PORTS

REGISTER 26-6: DDPCON: DEBUG DATA PORT CONTROL REGISTER

Legend:

R = Readable bit
W = Writable bit
P = Programmable bit
r = Reserved bit
U = Unimplemented bit
-n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)

bit 31-8 Reserved: Write ‘0’; ignore read
bit 7 DDPUSB: Debug Data Port Enable for USB bit
  1 = USB peripheral ignores USBFRZ (U1CNFG1<5>) setting
  0 = USB peripheral follows USBFRZ setting
bit 6 DDPU1: Debug Data Port Enable for UART1 bit
  1 = UART1 peripheral ignores FRZ (U1MODE<14>) setting
  0 = UART1 peripheral follows FRZ setting
bit 5 DDPU2: Debug Data Port Enable for UART2 bit
  1 = UART2 peripheral ignores FRZ (U2MODE<14>) setting
  0 = UART2 peripheral follows FRZ setting
bit 4 DDPSPI1: Debug Data Port Enable for SPI1 bit
  1 = SPI1 peripheral ignores FRZ (SPI1CON<14>) setting
  0 = SPI1 peripheral follows FRZ setting
bit 3 JTGEN: JTAG Port Enable bit
  1 = Enable JTAG Port
  0 = Disable JTAG Port
bit 2 TROEN: Trace Output Enable bit
  1 = Enable Trace Port
  0 = Disable Trace Port
bit 1-0 Reserved: Write ‘1’; ignore read