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12.0 I/O PORTS

Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 12. “I/O Ports” (DS61120) of the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).

2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information.

General purpose I/O pins are the simplest of peripherals. They allow the PIC® MCU to monitor and control other devices. To add flexibility and functionality, some pins are multiplexed with alternate function(s). These functions depend on which peripheral features are on the device. In general, when a peripheral is functioning, that pin may not be used as a general purpose I/O pin.

Following are some of the key features of this module:

Individual Output Pin Open-drain Enable/Disable
Individual Input Pin Weak Pull-up Enable/Disable
Monitor Selective Inputs and Generate Interrupt when Change in Pin State is Detected
Operation during CPU Sleep and Idle modes
Fast Bit Manipulation using CLR, SET and INV Registers

Figure 12-1 illustrates a block diagram of a typical multiplexed I/O port.

FIGURE 12-1: BLOCK DIAGRAM OF A TYPICAL MULTIPLEXED PORT STRUCTURE

Figure from the manual

Legend: R = Peripheral input buffer types may vary. Refer to Table 1-1 for peripheral details. Note: This block diagram is a general representation of a shared port/peripheral structure for illustration purposes only. The actual structure for any specific port/peripheral combination may be different than it is shown here.

12.1 Parallel I/O (PIO) Ports

All port pins have three registers (TRIS, LAT and PORT) that are directly associated with their operation.

TRIS is a data direction or tri-state control register that determines whether a digital pin is an input or an output. Setting a TRISx register bit = 1 configures the corresponding I/O pin as an input; setting a TRISx register bit = 0 configures the corresponding I/O pin as an output. All port I/O pins are defined as inputs after a device Reset. Certain I/O pins are shared with analog peripherals and default to analog inputs after a device Reset.

PORT is a register used to read the current state of the signal applied to the port I/O pins. Writing to a PORTx register performs a write to the port's latch, LATx register, latching the data to the port's I/O pins.

LAT is a register used to write data to the port I/O pins. The LATx latch register holds the data written to either the LATx or PORTx registers. Reading the LATx latch register reads the last value written to the corresponding port or latch register.

Not all port I/O pins are implemented on some devices, therefore, the corresponding PORTx, LATx and TRISx register bits will read as zeros.

12.1.1 CLR, SET AND INV REGISTERS

Every I/O module register has a corresponding CLR (clear), SET (set) and INV (invert) register designed to provide fast atomic bit manipulations. As the name of the register implies, a value written to a SET, CLR or INV register effectively performs the implied operation, but only on the corresponding base register and only bits specified as '1' are modified. Bits specified as '0' are not modified.

Reading SET, CLR and INV registers returns undefined values. To see the affects of a write operation to a SET, CLR or INV register, the base register must be read.

Note: Using a PORTxINV register to toggle a bit is recommended because the operation is performed in hardware atomically, using fewer instructions as compared to the traditional read-modify-write method shown below: PORTC ^= 0x0001;

12.1.2 DIGITAL INPUTS

Pins are configured as digital inputs by setting the corresponding TRIS register bits = 1. When configured as inputs, they are either TTL buffers or Schmitt Triggers. Several digital pins share functionality with analog inputs and default to the analog inputs at POR. Setting the corresponding bit in the AD1PCFG register = 1 enables the pin as a digital pin.

The maximum input voltage allowed on the input pins is the same as the maximum $V_{IH}$ specification. Refer to Section 29.0 "Electrical Characteristics" for $V_{IH}$ specification details.

Note: Analog levels on any pin that is defined as a digital input (including the ANx pins) may cause the input buffer to consume current that exceeds the device specifications.

12.1.3 ANALOG INPUTS

Certain pins can be configured as analog inputs used by the ADC and Comparator modules. Setting the corresponding bits in the AD1PCFG register = 0 enables the pin as an analog input pin and must have the corresponding TRIS bit set = 1 (input). If the TRIS bit is cleared = 0 (output), the digital output level ($V_{OH}$ or $V_{OL}$) will be converted. Any time a port I/O pin is configured as analog, its digital input is disabled and the corresponding PORTx register bit will read '0'. The AD1PCFG Register has a default value of 0x0000; therefore, all pins that share ANx functions are analog (not digital) by default.

12.1.4 DIGITAL OUTPUTS

Pins are configured as digital outputs by setting the corresponding TRIS register bits = 0. When configured as digital outputs, these pins are CMOS drivers or can be configured as open drain outputs by setting the corresponding bits in the ODCx Open-Drain Configuration register.

The open-drain feature allows the generation of outputs higher than $V_{DD}$ (e.g., 5V) on any desired 5V tolerant pins by using external pull-up resistors. The maximum open-drain voltage allowed is the same as the maximum $V_{IH}$ specification.

See the "Pin Diagrams" section for the available pins and their functionality.

12.1.5 ANALOG OUTPUTS

Certain pins can be configured as analog outputs, such as the CVREF output voltage used by the comparator module. Configuring the Comparator Reference module to provide this output will present the analog output voltage on the pin, independent of the TRIS register setting for the corresponding pin.

12.1.6 INPUT CHANGE NOTIFICATION

The input change notification function of the I/O ports (CNx) allows devices to generate interrupt requests in response to change of state on selected pin.

Each CNx pin also has a weak pull-up, which acts as a current source connected to the pin. The pull-ups are enabled by setting corresponding bit in CNPUE register.

13.0 TIMER1

Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 14. “Timers” (DS61105) of the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).

This family of PIC32MX devices features one synchronous/asynchronous 16-bit timer that can operate as a free-running interval timer for various timing applications and counting external events. This timer can also be used with the Secondary Oscillator (Sosc) for real-time clock applications. The following modes are supported:

Synchronous Internal Timer
Synchronous Internal Gated Timer
Synchronous External Timer
Asynchronous External Timer

13.1 Additional Supported Features

Selectable clock prescaler
Timer operation during CPU Idle and Sleep mode
Fast bit manipulation using CLR, SET and INV registers
Asynchronous mode can be used with the Sosc to function as a Real-Time Clock (RTC)

FIGURE 13-1: TIMER1 BLOCK DIAGRAM(1)

Figure from the manual

Note 1: The default state of the SOSCEN (OSCCON<1>) during a device Reset is controlled by the FSOSCEN bit in Configuration Word DEVCFG1.

NOTES:

14.0 TIMER2/3 AND TIMER4/5

Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 14. “Timers” (DS61105) of the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).

2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information.

This family of PIC32MX devices features four synchronous 16-bit timers (default) that can operate as a free-running interval timer for various timing applications and counting external events. The following modes are supported:

Synchronous Internal 16-bit Timer
Synchronous Internal 16-bit Gated Timer
Synchronous External 16-bit Timer

Two 32-bit synchronous timers are available by combining Timer2 with Timer3 and Timer4 with Timer5. The 32-bit timers can operate in three modes:

Synchronous Internal 32-bit Timer
Synchronous Internal 32-bit Gated Timer
Synchronous External 32-bit Timer

Note: Throughout this chapter, references to registers TxCON, TMRx and PRx use ‘x’ to represent Timer2 through 5 in 16-bit modes. In 32-bit modes, ‘x’ represents Timer2 or 4; ‘y’ represents Timer3 or 5.

14.1 Additional Supported Features

Selectable clock prescaler
Timers operational during CPU Idle
Time base for input capture and output compare modules (Timer2 and Timer3 only)
ADC event trigger (Timer3 only)
Fast bit manipulation using CLR, SET and INV registers

FIGURE 14-1: TIMER2, 3, 4, 5 BLOCK DIAGRAM (16-BIT)

Figure from the manual

Note 1: ADC event trigger is available on Timer3 only.
2: TxCK pins not available on 64-pin devices.

FIGURE 14-2: TIMER2/3, 4/5 BLOCK DIAGRAM (32-BIT)

Figure from the manual

Note 1: In this diagram, the use of 'x' in registers TxCON, TMRx, PRx and TxCK refers to either Timer2 or Timer4; the use of 'y' in registers TyCON, TMRy, PRy and TyIF refers to either Timer3 or Timer5. 2: TxCK pins are not available on 64-pin devices. 3: ADC event trigger is available only on Timer2/3 pair.

15.0 INPUT CAPTURE

Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 15. “Input Capture” (DS61122) of the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).

The Input Capture module is useful in applications requiring frequency (period) and pulse measurement. The PIC32MX3XX/4XX devices support up to five input capture channels.

The Input Capture module captures the 16-bit or 32-bit value of the selected Time Base registers when an event occurs at the ICx pin. The events that cause a capture event are listed below in three categories:

Simple Capture Event modes
- Capture timer value on every falling edge of input at ICx pin
- Capture timer value on every rising edge of input at ICx pin
Capture timer value on every edge (rising and falling)
Capture timer value on every edge (rising and falling), specified edge first.
Prescaler Capture Event modes
- Capture timer value on every 4th rising edge of input at ICx pin
- Capture timer value on every 16th rising edge of input at ICx pin

Each input capture channel can select between one of two 16-bit timers (Timer2 or Timer3) for the time base, or two 16-bit timers (Timer2 and Timer3) together to form a 32-bit timer. The selected timer can use either an internal or external clock.

Other operational features include:

Device wake-up from capture pin during CPU Sleep and Idle modes
Interrupt on input capture event
4-word FIFO buffer for capture values
- Interrupt optionally generated after 1, 2, 3 or 4 buffer locations are filled
Input capture can also be used to provide additional sources of external interrupts

FIGURE 15-1: INPUT CAPTURE BLOCK DIAGRAM

Figure from the manual

NOTES:

16.0 OUTPUT COMPARE

Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 16. “Output Compare” (DS61111) of the PIC32 Family Reference Manual, which is available from the Microchip web site (www.microchip.com/PIC32).

The Output Compare module (OCMP) is used to generate a single pulse or a train of pulses in response to selected time base events. For all modes of operation, the OCMP module compares the values stored in the OCxR and/or the OCxRS registers to the value in the selected timer. When a match occurs, the OCMP module generates an event based on the selected mode of operation.

The following are some of the key features:

Multiple output compare modules in a device
Programmable interrupt generation on compare event
Single and Dual Compare modes
Single and continuous output pulse generation
Pulse-Width Modulation (PWM) mode
Hardware-based PWM Fault detection and automatic output disable
Programmable selection of 16-bit or 32-bit time bases.
Can operate from either of two available 16-bit time bases or a single 32-bit time base

FIGURE 16-1: OUTPUT COMPARE MODULE BLOCK DIAGRAM

Figure from the manual

Note 1: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare channels 1 through 5. 2: The OCFA pin controls the OC1-OC4 channels. The OCFB pin controls the OC5 channel. 3: Each output compare channel can use one of two selectable 16-bit time bases or a single 32-bit timer base.

NOTES:

17.0 SERIAL PERIPHERAL INTERFACE (SPI)

Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 23. “Serial Peripheral Interface (SPI)” (DS61106) of the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).

The SPI module is a synchronous serial interface useful for communicating with external peripherals and other microcontroller devices. These peripheral devices may be Serial EEPROMs, shift registers, display drivers, Analog-to-Digital Converters, etc. The PIC32MX SPI module is compatible with Motorola® SPI and SIOP interfaces.

Following are some of the key features of this module:

Master and Slave Modes Support
Four Different Clock Formats
Framed SPI Protocol Support
User Configurable 8-bit, 16-bit and 32-bit Data Width
Separate SPI Data Registers for Receive and Transmit
Programmable Interrupt Event on every 8-bit, 16-bit and 32-bit Data Transfer
Operation during CPU Sleep and Idle Mode
Fast Bit Manipulation using CLR, SET and INV Registers

FIGURE 17-1: SPI MODULE BLOCK DIAGRAM

Figure from the manual

Note: Access SPIxTXB and SPIxRXB registers via SPIxBUF register.

NOTES:

18.0 INTER-INTEGRATED CIRCUIT™ (I²C™)

Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 24. “Inter-Integrated Circuit (I²C™)” (DS61116) of the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).

The I²C module provides complete hardware support for both Slave and Multi-Master modes of the I²C serial communication standard. Figure 18-1 illustrates the I²C module block diagram.

The PIC32MX3XX/4XX devices have up to two I²C interface modules, denoted as I2C1 and I2C2. Each I²C module has a 2-pin interface: the SCLx pin is clock and the SDAx pin is data.

Each I²C module, ‘I2Cx’ (x = 1 or 2), offers the following key features:

I²C Interface Supporting both Master and Slave Operation.
I²C Slave Mode Supports 7 and 10-bit Address.
I²C Master Mode Supports 7 and 10-bit Address.
I²C Port allows Bidirectional Transfers between Master and Slaves.
Serial Clock Synchronization for I²C Port can be used as a Handshake Mechanism to Suspend and Resume Serial Transfer (SCLREL control).
I²C Supports Multi-master Operation; Detects Bus Collision and Arbitrates Accordingly.
Provides Support for Address Bit Masking.

FIGURE 18-1: I²C™ BLOCK DIAGRAM (x = 1 OR 2)

19.0 UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART)

Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 21. “Universal Asynchronous Receiver Transmitter (UART)” (DS61107) of the PIC32 Family Reference Manual, which is available from the Microchip web site (www.microchip.com/PIC32).

The UART module is one of the serial I/O modules available in PIC32MX3XX/4XX family devices. The UART is a full-duplex, asynchronous communication channel that communicates with peripheral devices and personal computers through protocols such as RS-232, RS-485, LIN 1.2 and IrDA®. The module also supports the hardware flow control option, with UxCTS and UxRTS pins, and also includes an IrDA encoder and decoder.

The primary features of the UART module are:

Full-duplex, 8-bit or 9-bit data transmission
Even, odd or no parity options (for 8-bit data)
One or two Stop bits
Hardware auto-baud feature
Hardware flow control option
Fully integrated Baud Rate Generator (BRG) with 16-bit prescaler
Baud rates ranging from 76 bps to 20 Mbps at 80 MHz
4-level-deep First-In-First-Out (FIFO) Transmit Data Buffer
4-level-deep FIFO Receive Data Buffer
Parity, framing and buffer overrun error detection
Support for interrupt only on address detect (9th bit = 1)
Separate transmit and receive interrupts
Loopback mode for diagnostic support
LIN protocol support
IrDA encoder and decoder with 16x baud clock output for external IrDA encoder/decoder support

Figure 19-1 illustrates a simplified block diagram of the UART.

FIGURE 19-1: UART SIMPLIFIED BLOCK DIAGRAM

Figure from the manual

FIGURE 19-2: TRANSMISSION (8-BIT OR 9-BIT DATA)

Figure from the manual

FIGURE 19-3: TWO CONSECUTIVE TRANSMISSIONS

Figure from the manual

FIGURE 19-4: UART RECEPTION

Figure from the manual

Note: This timing diagram shows 2 characters received on the UxRX input.

FIGURE 19-5: UART RECEPTION WITH RECEIVE OVERRUN

Figure from the manual

Note: This diagram shows 6 characters received without the user reading the input buffer. The 5th character received is held in the Receive Shift register. An overrun error occurs at the start of the 6th character.