Microchip PIC32 datasheet: 27.0 Instruction set

Published by Microchip · pages 141–160 of 214 · Original PDF

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27.0 INSTRUCTION SET

The PIC32MX3XX/4XX family instruction set complies with the MIPS32 Release 2 instruction set architecture. PIC32MX does not support the following features:

  • CoreExtend instructions
  • Coprocessor 1 instructions
  • Coprocessor 2 instructions

Table 27-1 provides a summary of the instructions that are implemented by the PIC32MX3XX/4XX family core.

Note: Refer to “MIPS32® Architecture for Programmers Volume II: The MIPS32® Instruction Set” at www.mips.com for more information.

TABLE 27-1: MIPS32® INSTRUCTION SET

Instruction Description Function
ADD Integer Add Rd = Rs + Rt
ADDI Integer Add Immediate Rt = Rs + Immed
ADDIU Unsigned Integer Add Immediate Rt = Rs +ᵤ Immed
ADDU Unsigned Integer Add Rd = Rs +ᵤ Rt
AND Logical AND Rd = Rs & Rt
ANDI Logical AND Immediate Rt = Rs & (0₁₆ \ \ Immed)
B Unconditional Branch (Assembler idiom for: BEQ r0, r0, offset) PC += (int)offset
BAL Branch and Link (Assembler idiom for: BGEZAL r0, offset) GPR[31] = PC + 8PC += (int)offset
BEQ Branch on Equal if Rs == RtPC += (int)offset
BEQL Branch on Equal Likely⁽¹⁾ if Rs == RtPC += (int)offsetelseIgnore Next Instruction
BGEZ Branch on Greater Than or Equal to Zero if !Rs[31]PC += (int)offset
BGEZAL Branch on Greater Than or Equal to Zero and Link GPR[31] = PC + 8if !Rs[31]PC += (int)offset
BGEZALL Branch on Greater Than or Equal to Zero and Link Likely⁽¹⁾ GPR[31] = PC + 8if !Rs[31]PC += (int)offsetelseIgnore Next Instruction
BGEZL Branch on Greater Than or Equal to Zero Likely⁽¹⁾ if !Rs[31]PC += (int)offsetelseIgnore Next Instruction
BGTZ Branch on Greater Than Zero if !Rs[31] && Rs != 0PC += (int)offset
BGTZL Branch on Greater Than Zero Likely⁽¹⁾ if !Rs[31] && Rs != 0PC += (int)offsetelseIgnore Next Instruction
BLEZ Branch on Less Than or Equal to Zero if Rs[31] \ \ Rs == 0PC += (int)offset

Note 1: This instruction is deprecated and should not be used.

TABLE 27-1: MIPS32® INSTRUCTION SET (CONTINUED)

Instruction Description Function
BLEZL Branch on Less Than or Equal to Zero Likely(1) if Rs[31] \ \ Rs == 0PC += (int)offsetelseIgnore Next Instruction
BLTZ Branch on Less Than Zero if Rs[31]PC += (int)offset
BLTZAL Branch on Less Than Zero and Link GPR[31] = PC + 8if Rs[31]PC += (int)offset
BLTZALL Branch on Less Than Zero and Link Likely(1) GPR[31] = PC + 8if Rs[31]PC += (int)offsetelseIgnore Next Instruction
BLTZL Branch on Less Than Zero Likely(1) if Rs[31]PC += (int)offsetelseIgnore Next Instruction
BNE Branch on Not Equal if Rs != RtPC += (int)offset
BNEL Branch on Not Equal Likely(1) if Rs != RtPC += (int)offsetelseIgnore Next Instruction
BREAK Breakpoint Break Exception
CLO Count Leading Ones Rd = NumLeadingOnes(Rs)
CLZ Count Leading Zeroes Rd = NumLeadingZeroes(Rs)
DERET Return from Debug Exception PC = DEPCExit Debug Mode
DI Atomically Disable Interrupts Rt = Status; StatusIE = 0
DIV Divide LO = (int)Rs / (int)RtHI = (int)Rs % (int)Rt
DIVU Unsigned Divide LO = (uns)Rs / (uns)RtHI = (uns)Rs % (uns)Rt
EHB Execution Hazard Barrier Stop instruction executionuntil execution hazards arecleared
EI Atomically Enable Interrupts Rt = Status; StatusIE = 1
ERET Return from Exception if StatusERLPC = ErrorEPCelsePC = EPCStatusEXL = 0StatusERL = 0LL = 0
EXT Extract Bit Field Rt = ExtractField(Rs, pos,size)
INS Insert Bit Field Rt = InsertField(Rs, Rt, pos,size)
J Unconditional Jump PC = PC[31:28] \ \ offset<<2

Note 1: This instruction is deprecated and should not be used.

DS61143H-page 142 © 2011 Microchip Technology Inc.

TABLE 27-1: MIPS32® INSTRUCTION SET (CONTINUED)

Instruction Description Function
JAL Jump and Link GPR[31] = PC + 8PC = PC[31:28] \ \ offset<<2
JALR Jump and Link Register Rd = PC + 8PC = Rs
JALR.HB Jump and Link Register with Hazard Barrier Like JALR, but also clears execution and instruction hazards
JR Jump Register PC = Rs
JR.HB Jump Register with Hazard Barrier Like JR, but also clears execution and instruction hazards
LB Load Byte Rt = (byte)Mem[Rs+offset]
LBU Unsigned Load Byte Rt = (ubyte))Mem[Rs+offset]
LH Load Halfword Rt = (half)Mem[Rs+offset]
LHU Unsigned Load Halfword Rt = (uhalf)Mem[Rs+offset]
LL Load Linked Word Rt = Mem[Rs+offset>LLbit = 1LLAdr = Rs + offset
LUI Load Upper Immediate Rt = immediate << 16
LW Load Word Rt = Mem[Rs+offset]
LWPC Load Word, PC relative Rt = Mem[PC+offset]
LWL Load Word Left Re = Re MERGE Mem[Rs+offset]
LWR Load Word Right Re = Re MERGE Mem[Rs+offset]
MADD Multiply-Add HI \ LO += (int)Rs * (int)Rt
MADDU Multiply-Add Unsigned HI \ LO += (uns)Rs * (uns)Rt
MFC0 Move from Coprocessor 0 Rt = CPR[0, Rd, sel]
MFHI Move from HI Rd = HI
MFLO Move from LO Rd = LO
MOVN Move Conditional on Not Zero if Rt ≠ 0 thenRd = Rs
MOVZ Move Conditional on Zero if Rt = 0 thenRd = Rs
MSUB Multiply-Subtract HI \ LO -= (int)Rs * (int)Rt
MSUBU Multiply-Subtract Unsigned HI \ LO -= (uns)Rs * (uns)Rt
MTC0 Move to Coprocessor 0 CPR[0, n, Sel] = Rt
MTHI Move to HI HI = Rs
MTLO Move to LO LO = Rs
MUL Multiply with register write HI \ LO =UnpredictableRd = ((int)Rs * (int)Rt)31..0
MULT Integer Multiply HI \ LO = (int)Rs * (int)Rd
MULTU Unsigned Multiply HI \ LO = (uns)Rs * (uns)Rd
NOP No Operation(Assembler idiom for: SLL r0, r0, r0)
NOR Logical NOR Rd = ~(Rs \ Rt)
OR Logical OR Rd = Rs \ Rt
ORI Logical OR Immediate Rt = Rs \ Immed
RDHWR Read Hardware Register (if enabled by HWREna Register) Re = HWR[Rd]

Note 1: This instruction is deprecated and should not be used.

TABLE 27-1: MIPS32® INSTRUCTION SET (CONTINUED)

Instruction Description Function
RDPGPR Read GPR from Previous Shadow Set Rt = SGPR[SRSCtlPSS, Rd]
ROTR Rotate Word Right Rd = Rtsa-1..0 \ \ Rt31..sa
ROTRV Rotate Word Right Variable Rd = RtRs-1..0 \ \ Rt31..Rs
SB Store Byte (byte)Mem[Rs+offset] = Rt
SC Store Conditional Word if LLbit = 1mem[Rs+offset> = RtRt = LLbit
SDBBP Software Debug Break Point Trap to SW Debug Handler
SEB Sign-Extend Byte Rd = SignExtend (Rs-7...0)
SEH Sign-Extend Half Rd = SignExtend (Rs-15...0)
SH Store Half (half)Mem[Rs+offset> = Rt
SLL Shift Left Logical Rd = Rt << sa
SLLV Shift Left Logical Variable Rd = Rt << Rs[4:0]
SLT Set on Less Than if (int)Rs < (int)RtRd = 1elseRd = 0
SLTI Set on Less Than Immediate if (int)Rs < (int)ImmedRt = 1elseRt = 0
SLTIU Set on Less Than Immediate Unsigned if (uns)Rs < (uns)ImmedRt = 1elseRt = 0
SLTU Set on Less Than Unsigned if (uns)Rs < (uns)ImmedRd = 1elseRd = 0
SRA Shift Right Arithmetic Rd = (int)Rt >> sa
SRAV Shift Right Arithmetic Variable Rd = (int)Rt >> Rs[4:0]
SRL Shift Right Logical Rd = (uns)Rt >> sa
SRLV Shift Right Logical Variable Rd = (uns)Rt >> Rs[4:0]
SSNOP Superscalar Inhibit No Operation NOP
SUB Integer Subtract Rt = (int)Rs - (int)Rd
SUBU Unsigned Subtract Rt = (uns)Rs - (uns)Rd
SW Store Word Mem[Rs+offset] = Rt
SWL Store Word Left Mem[Rs+offset] = Rt
SWR Store Word Right Mem[Rs+offset] = Rt
SYNC Synchronize Orders the cached coherent and uncached loads and stores for access to the shared memory
SYSCALL System Call SystemCallException
TEQ Trap if Equal if Rs == RtTrapException
TEQI Trap if Equal Immediate if Rs == (int)ImmedTrapException

Note 1: This instruction is deprecated and should not be used.

TABLE 27-1: MIPS32® INSTRUCTION SET (CONTINUED)

Instruction Description Function
TGE Trap if Greater Than or Equal if (int)Rs >= (int)RtTrapException
TGEI Trap if Greater Than or Equal Immediate if (int)Rs >= (int)ImmedTrapException
TGEIU Trap if Greater Than or Equal Immediate Unsigned if (uns)Rs >= (uns)ImmedTrapException
TGEU Trap if Greater Than or Equal Unsigned if (uns)Rs >= (uns)RtTrapException
TLT Trap if Less Than if (int)Rs < (int)RtTrapException
TLT I Trap if Less Than Immediate if (int)Rs < (int)ImmedTrapException
TLT IU Trap if Less Than Immediate Unsigned if (uns)Rs < (uns)ImmedTrapException
TLTU Trap if Less Than Unsigned if (uns)Rs < (uns)RtTrapException
TNE Trap if Not Equal if Rs != RtTrapException
TNEI Trap if Not Equal Immediate if Rs != (int)ImmedTrapException
WAIT Wait for Interrupt Go to a low power mode and stall untilinterrupt occurs
WRPGPR Write to GPR in Previous Shadow Set SGPR[SRSCtl_pss, Rd> = Rt
WSBH Word Swap Bytes Within Halfwords Rd = Rt₂₃..₁₆ \ \ Rt₃₁..₂₄ \ \ Rt₇..₀\ \ Rt₁₅..₈
XOR Exclusive OR Rd = Rs ^ Rt
XORI Exclusive OR Immediate Rt = Rs ^ (uns)Immed

Note 1: This instruction is deprecated and should not be used.

NOTES:

28.0 DEVELOPMENT SUPPORT

The PIC® microcontrollers and dsPIC® digital signal controllers are supported with a full range of software and hardware development tools:

  • Integrated Development Environment
    • MPLAB® IDE Software
  • Compilers/Assemblers/Linkers
    • MPLAB C Compiler for Various Device Families
    • HI-TECH C for Various Device Families
    • MPASM™ Assembler
    • MPLINK™ Object Linker/ MPLIB™ Object Librarian
    • MPLAB Assembler/Linker/Librarian for Various Device Families
  • Simulators
    • MPLAB SIM Software Simulator
  • Emulators
    • MPLAB REAL ICE™ In-Circuit Emulator
  • In-Circuit Debuggers
    • MPLAB ICD 3
    • PICkit™ 3 Debug Express
  • Device Programmers
    • PICkit™ 2 Programmer
    • MPLAB PM3 Device Programmer
  • Low-Cost Demonstration/Development Boards, Evaluation Kits, and Starter Kits

28.1 MPLAB Integrated Development Environment Software

The MPLAB IDE software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market. The MPLAB IDE is a Windows® operating system-based application that contains:

  • A single graphical interface to all debugging tools
    • Simulator
    • Programmer (sold separately)
    • In-Circuit Emulator (sold separately)
    • In-Circuit Debugger (sold separately)
  • A full-featured editor with color-coded context
  • A multiple project manager
  • Customizable data windows with direct edit of contents
  • High-level source code debugging
  • Mouse over variable inspection
  • Drag and drop variables from source to watch windows
  • Extensive on-line help
  • Integration of select third party tools, such as IAR C Compilers

The MPLAB IDE allows you to:

  • Edit your source files (either C or assembly)
  • One-touch compile or assemble, and download to emulator and simulator tools (automatically updates all project information)
  • Debug using:
    • Source files (C or assembly)
    • Mixed C and assembly
    • Machine code

MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power.

28.2 MPLAB C Compilers for Various Device Families

The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use.

For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger.

28.3 HI-TECH C for Various Device Families

The HI-TECH C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC family of microcontrollers and the dsPIC family of digital signal controllers. These compilers provide powerful integration capabilities, omniscient code generation and ease of use.

For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger.

The compilers include a macro assembler, linker, preprocessor, and one-step driver, and can run on multiple platforms.

28.4 MPASM Assembler

The MPASM Assembler is a full-featured, universal macro assembler for PIC10/12/16/18 MCUs.

The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging.

The MPASM Assembler features include:

  • Integration into MPLAB IDE projects
  • User-defined macros to streamline assembly code
  • Conditional assembly for multi-purpose source files
  • Directives that allow complete control over the assembly process

28.5 MPLINK Object Linker/ MPLIB Object Librarian

The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler. It can link relocatable objects from precompiled libraries, using directives from a linker script.

The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications.

The object linker/library features include:

  • Efficient linking of single libraries instead of many smaller files
  • Enhanced code maintainability by grouping related modules together
  • Flexible creation of libraries with easy module listing, replacement, deletion and extraction

28.6 MPLAB Assembler, Linker and Librarian for Various Device Families

MPLAB Assembler produces relocatable machine code from symbolic assembly language for PIC24, PIC32 and dsPIC devices. MPLAB C Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include:

  • Support for the entire device instruction set
  • Support for fixed-point and floating-point data
  • Command line interface
  • Rich directive set
  • Flexible macro language
  • MPLAB IDE compatibility

DS61143H-page 148 © 2011 Microchip Technology Inc.

28.7 MPLAB SIM Software Simulator

The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, most peripherals and internal registers.

The MPLAB SIM Software Simulator fully supports symbolic debugging using the MPLAB C Compilers, and the MPASM and MPLAB Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool.

28.8 MPLAB REAL ICE In-Circuit Emulator System

MPLAB REAL ICE In-Circuit Emulator System is Microchip’s next generation high-speed emulator for Microchip Flash DSC and MCU devices. It debugs and programs PIC® Flash MCUs and dsPIC® Flash DSCs with the easy-to-use, powerful graphical user interface of the MPLAB Integrated Development Environment (IDE), included with each kit.

The emulator is connected to the design engineer’s PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with in-circuit debugger systems (RJ11) or with the new high-speed, noise tolerant, Low-Voltage Differential Signal (LVDS) interconnection (CAT5).

The emulator is field upgradable through future firmware downloads in MPLAB IDE. In upcoming releases of MPLAB IDE, new devices will be supported, and new features will be added. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables.

28.9 MPLAB ICD 3 In-Circuit Debugger System

MPLAB ICD 3 In-Circuit Debugger System is Microchip’s most cost effective high-speed hardware debugger/programmer for Microchip Flash Digital Signal Controller (DSC) and microcontroller (MCU) devices. It debugs and programs PIC® Flash microcontrollers and dsPIC® DSCs with the powerful, yet easy-to-use graphical user interface of MPLAB Integrated Development Environment (IDE).

The MPLAB ICD 3 In-Circuit Debugger probe is connected to the design engineer’s PC using a high-speed USB 2.0 interface and is connected to the target with a connector compatible with the MPLAB ICD 2 or MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3 supports all MPLAB ICD 2 headers.

28.10 PICkit 3 In-Circuit Debugger/Programmer and PICkit 3 Debug Express

The MPLAB PICkit 3 allows debugging and programming of PIC® and dsPIC® Flash microcontrollers at a most affordable price point using the powerful graphical user interface of the MPLAB Integrated Development Environment (IDE). The MPLAB PICkit 3 is connected to the design engineer’s PC using a full speed USB interface and can be connected to the target via an Microchip debug (RJ-11) connector (compatible with MPLAB ICD 3 and MPLAB REAL ICE). The connector uses two device I/O pins and the reset line to implement in-circuit debugging and In-Circuit Serial Programming™.

The PICkit 3 Debug Express include the PICkit 3, demo board and microcontroller, hookup cables and CDROM with user’s guide, lessons, tutorial, compiler and MPLAB IDE software.

28.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express

The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers. The full featured Windows® programming interface supports baseline (PIC10F, PIC12F5xx, PIC16F5xx), midrange (PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30, dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit microcontrollers, and many Microchip Serial EEPROM products. With Microchip’s powerful MPLAB Integrated Development Environment (IDE) the PICkit™ 2 enables in-circuit debugging on most PIC® microcontrollers. In-Circuit-Debugging runs, halts and single steps the program while the PIC microcontroller is embedded in the application. When halted at a breakpoint, the file registers can be examined and modified.

The PICkit 2 Debug Express include the PICkit 2, demo board and microcontroller, hookup cables and CDROM with user’s guide, lessons, tutorial, compiler and MPLAB IDE software.

28.12 MPLAB PM3 Device Programmer

The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modular, detachable socket assembly to support various package types. The ICSP™ cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an MMC card for file storage and data applications.

28.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits

A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification.

The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory.

The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications.

In addition to the PICDEM™ and dsPICDEM™ demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ® security ICs, CAN, IrDA®, PowerSmart battery management, SEEVAL® evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more.

Also available are starter kits that contain everything needed to experience the specified device. This usually includes a single application and debug capability, all on one board.

Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits.

29.0 ELECTRICAL CHARACTERISTICS

This section provides an overview of PIC32MX3XX/4XX electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available.

Absolute maximum ratings for the PIC32MX3XX/4XX are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at these or any other conditions above the parameters indicated in the operation listings of this specification is not implied.

Absolute Maximum Ratings (Note 1)

  • Ambient temperature under bias ........ -40°C to +105°C
  • Storage temperature ........ -65°C to +150°C
  • Voltage on VDD with respect to VSS ........ -0.3V to +4.0V Voltage on any pin that is not 5V tolerant, with respect to VSS (Note 3) ... -0.3V to (VDD + 0.3V)
    Voltage on any 5V tolerant pin with respect to VSS when VDD ≥ 2.3V (Note 3) ... -0.3V to +5.5V
    Voltage on any 5V tolerant pin with respect to VSS when VDD < 2.3V (Note 3) ... -0.3V to +3.6V
  • Voltage on VCORE with respect to VSS ........ -0.3V to 2.0V
  • Voltage on VBUS with respect to VSS ........ -0.3V to +5.5V
  • Maximum current out of Vss pin(s) ........ 300 mA
  • Maximum current into VDD pin(s) (Note 2) ........ 300 mA
  • Maximum output current sunk by any I/O pin ........ 25 mA
  • Maximum output current sourced by any I/O pin ........ 25 mA
  • Maximum current sink by all ports ........ 200 mA
  • Maximum current sourced by all ports (Note 2) ........ 200 mA

Note 1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
2: Maximum allowable current is a function of device maximum power dissipation (see Table 29-2).
3: See the “Pin Diagrams” section for the 5V tolerant pins.


29.1 DC Characteristics

TABLE 29-1: OPERATING MIPS VS. VOLTAGE

Characteristic VDD Range (in Volts) Temp. Range (in °C) Max. Frequency PIC32MX3XX/4XX
DC5 2.3V-3.6V -40°C to +85°C 80 MHz (Note 1)
DC5b 2.3V-3.6V -40°C to +105°C 80 MHz (Note 1)

Note 1: 40 MHz maximum for PIC32MX320F032H and PIC32MX420F032H devices.

TABLE 29-2: THERMAL OPERATING CONDITIONS

Rating Symbol Min. Typical Max. Unit
Industrial Temperature Devices
Operating Junction Temperature Range TJ -40 — +125 °C
Operating Ambient Temperature Range TA -40 — +85 °C
V-Temp Temperature Devices
Operating Junction Temperature Range TJ -40 — +140 °C
Operating Ambient Temperature Range TA -40 — +105 °C
Power Dissipation: Internal Chip Power Dissipation: PINT = VDD x (IDD – S IOH) I/O Pin Power Dissipation: I/O = S ({VDD – VOH} x IOH) + S (VOL x IOL)) PD PINT + PI/O W
Maximum Allowed Power Dissipation PDMAX (TJ – TA)/θJA W

TABLE 29-3: THERMAL PACKAGING CHARACTERISTICS

Characteristics Symbol Typical Max. Unit Notes
Package Thermal Resistance, 121-Pin XBGA (10x10x1.1 mm) θJA 40 — °C/W 1
Package Thermal Resistance, 100-Pin TQFP (12x12x1 mm) θJA 43 — °C/W 1
Package Thermal Resistance, 64-Pin TQFP (10x10x1 mm) θJA 47 — °C/W 1
Package Thermal Resistance, 64-Pin QFN (9x9x0.9 mm) θJA 28 — °C/W 1

Note 1: Junction to ambient thermal resistance, Theta-JA (θJA) numbers are achieved by package simulations.

TABLE 29-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS

DC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-Temp
Param. No. Symbol Characteristics Min. Typical Max. Units Conditions
Operating Voltage
DC10 VDD Supply Voltage 2.3 — 3.6 V —
DC12 VDR RAM Data Retention Voltage (Note 1) 1.75 — — V —
DC16 VPOR VDD Start Voltage to Ensure Internal Power-on Reset Signal 1.75 — 1.95 V —
DC17 SVDD VDD Rise Rate to Ensure Internal Power-on Reset Signal 0.05 — — V/ms —

Note 1: This is the limit to which VDD can be lowered without losing RAM data.

TABLE 29-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD)

DC CHARACTERISTICS

Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +105°C for V-Temp

Param. No. Typical⁽³⁾ Max. Units Conditions
Operating Current (IDD)⁽¹,²⁾
DC20 8.5 13 mA Code executing from Flash -40°C, +25°C, +85°C — 4 MHz
9 15 +105°C
DC20c 4.0 — mA Code executing from SRAM —
DC21 23.5 32 mA Code executing from Flash — — 20 MHz (Note 4)
DC21c 16.4 — mA Code executing from SRAM — —
DC22 48 61 mA Code executing from Flash — — 60 MHz (Note 4)
DC22c 45 — mA Code executing from SRAM — —
DC23 55 75 mA Code executing from Flash -40°C, +25°C, +85°C 2.3V 80 MHz
60 100 +105°C
DC23c 55 — mA Code executing from SRAM — —
DC24 — 100 µA — -40°C 2.3V LPRC (31 kHz) (Note 4)
DC24a — 130 µA — +25°C
DC24b — 670 µA — +85°C
DC24c — 850 µA — +105°C
DC25 94 — µA — -40°C 3.3V
DC25a 125 — µA — +25°C
DC25b 302 — µA — +85°C
DC25d 400 — µA — +105°C
DC25c 71 — µA Code executing from SRAM — —
DC26 — 110 µA — -40°C 3.6V
DC26a — 180 µA — +25°C
DC26b — 700 µA — +85°C
DC26c — 900 µA — +105°C

Note 1: A device’s IDD supply current is mainly a function of the operating voltage and frequency. Other factors, such as PBCLK (Peripheral Bus Clock) frequency, number of peripheral modules enabled, internal code execution pattern, execution from program Flash memory vs. SRAM, I/O pin loading and switching rate, oscillator type as well as temperature can have an impact on the current consumption.

2: The test conditions for IDD measurements are as follows: Oscillator mode = EC+PLL with OSC1 driven by external square wave from rail to rail and PBCLK divisor = 1:8. CPU, Program Flash and SRAM data memory are operational, Program Flash memory Wait states = 7, program cache and prefetch are disabled and SRAM data memory Wait states = 1. All peripheral modules are disabled (ON bit = 0). WDT and FSCM are disabled. All I/O pins are configured as inputs and pulled to Vss. MCLR = VDD.

3: Data in “Typical” column is at 3.3V, 25°C at specified operating frequency unless otherwise stated. Parameters are for design guidance only and are not tested.

4: This parameter is characterized, but not tested in manufacturing.

TABLE 29-6: DC CHARACTERISTICS: IDLE CURRENT (IIdle)

DC CHARACTERISTICS

Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +105°C for V-Temp

Parameter No. Typical(2) Max. Units Conditions
Idle Current (IIdle): Core OFF, Clock ON Base Current (Note 1)
DC30 — 5 mA -40°C, +25°C, +85°C 2.3V 4 MHz
DC30a 1.4 — mA -40°C, +25°C, +85°C —
DC30b — 5 mA -40°C, +25°C, +85°C 3.6V
DC30c — 8 mA +105°C
DC31 — 15 mA -40°C, +25°C, +85°C 2.3V 20 MHz (Note 3)
DC31a 13 — mA -40°C, +25°C, +85°C —
DC31b — 17 mA -40°C, +25°C, +85°C 3.6V
DC31c — 25 mA +105°C
DC32 — 22 mA -40°C, +25°C, +85°C 2.3V 60 MHz (Note 3)
DC32a 20 — mA -40°C, +25°C, +85°C —
DC32b — 25 mA -40°C, +25°C, +85°C 3.6V
DC32c — 32 mA +105°C
DC33 — 29 mA -40°C, +25°C, +85°C 2.3V 80 MHz
DC33a 24 — mA -40°C, +25°C, +85°C —
DC33b — 32 mA -40°C, +25°C, +85°C 3.6V
DC33c — 40 mA +105°C
DC34 — 36 µA -40°C 2.3V LPRC (31 kHz) (Note 3)
DC34a — 62 µA +25°C
DC34b — 392 µA +85°C
DC34c — 550 µA +105°C
DC35 35 — µA -40°C 3.3V
DC35a 65 — µA +25°C
DC35b 242 — µA +85°C
DC35c 350 — µA +105°C
DC36 — 43 µA -40°C 3.6V
DC36a — 106 µA +25°C
DC36b — 414 µA +85°C
DC36c — 600 µA +105°C

Note 1: The test conditions for base IIdle current measurements are as follows: System clock is enabled and PBCLK divisor = 1:8. CPU in Idle mode (CPU core halted). Only digital peripheral modules are enabled (ON bit = 1) and being clocked. WDT and FSCM are disabled. All I/O pins are configured as inputs and pulled to Vss. MCLR = VDD.

2: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested.

3: This parameter is characterized, but not tested in manufacturing.

TABLE 29-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)

DC CHARACTERISTICS

Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +105°C for V-Temp

Parameter No. Typical(2) Max. Units Conditions
Power-Down Current (IPD)(1)
DC40 7 30 μA -40°C 2.3V Base Power-Down Current (Note 6)
DC40a 24 30 μA +25°C
DC40b 205 300 μA +85°C
DC40h 450 900 μA +105°C
DC40c 25 — μA +25°C 3.3V Base Power-Down Current
DC40d 9 70 μA -40°C 3.6V Base Power-Down Current
DC40e 25 70 μA +25°C
DC40g 115 200(5) μA +70°C
DC40f 200 400 μA +85°C
DC40i 470 1200 μA +105°C
Module Differential Current
DC41 — 10 μA -40°C 2.3V Watchdog Timer Current: ΔIWDT (Notes 3, 6)
DC41a — 10 μA +25°C
DC41b — 10 μA +85°C
DC41g — 12 μA +105°C
DC41c 5 — μA +25°C 3.3V Watchdog Timer Current: ΔIWDT (Note 3)
DC41d — 10 μA -40°C 3.6V Watchdog Timer Current: ΔIWDT (Note 3)
DC41e — 10 μA +25°C
DC41f — 12 μA +85°C
DC41h — 15 μA +105°C
DC42 — 10 μA -40°C 2.3V RTCC + Timer1 w/32 kHz Crystal: ΔIRTCC (Notes 3, 6)
DC42a — 17 μA +25°C
DC42b — 37 μA +85°C
DC42h — 45 μA +105°C
DC42c 23 — μA +25°C 3.3V RTCC + Timer1 w/32 kHz Crystal: ΔIRTCC (Note 3)
DC42e — 10 μA -40°C 3.6V RTCC + Timer1 w/32 kHz Crystal: ΔIRTCC (Note 3)
DC42f — 30 μA +25°C
DC42g — 44 μA +85°C
DC42i — 44 μA +105°C

Note 1: Base IPD is measured with all digital peripheral modules disabled. All I/Os are configured as inputs and pulled low. WDT and FSCM are disabled.
2: Data in the “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested.
3: The Δ current is the additional current consumed when the module is enabled. This current should be added to the base IPD current.
4: Test conditions for ADC module differential current are as follows: Internal ADC RC oscillator enabled.
5: Data is characterized at +70°C and not tested. Parameter is for design guidance only.
6: This parameter is characterized, but not tested in manufacturing.

TABLE 29-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) (CONTINUED)

DC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-Temp
Parameter No. Typical(2) Max. Units Conditions
Module Differential Current (Continued)
DC43 — 1100 μA -40°C 2.5V ADC: ΔIADC (Notes 3, 4, 6)
DC43a — 1100 μA +25°C
DC43b — 1000 μA +85°C
DC43h — 1200 μA +105°C
DC43c 880 — μA — — ADC: ΔIADC (Notes 3, 4)
DC43e — 1100 μA -40°C 3.6V ADC: ΔIADC (Notes 3, 4)
DC43f — 1100 μA +25°C
DC43g — 1000 μA +85°C
DC43i — 1200 μA +105°C

Note 1: Base IPD is measured with all digital peripheral modules disabled. All I/Os are configured as inputs and pulled low. WDT and FSCM are disabled.

2: Data in the “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested.

3: The Δ current is the additional current consumed when the module is enabled. This current should be added to the base IPD current.

4: Test conditions for ADC module differential current are as follows: Internal ADC RC oscillator enabled.

5: Data is characterized at +70°C and not tested. Parameter is for design guidance only.

6: This parameter is characterized, but not tested in manufacturing.

TABLE 29-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS

DC CHARACTERISTICS

Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +105°C for V-Temp

Param. No. Symbol Characteristics Min. Typical(1) Max. Units Conditions
DI10 VIL Input Low VoltageI/O pins:with TTL Bufferwith Schmitt Trigger BufferMCLROSC1 (XT mode)OSC1 (HS mode)SDAx, SCLxSDAx, SCLx VssVssVssVssVssVssVss ——————— 0.15 VDD0.2 VDD0.2 VDD0.2 VDD0.2 VDD0.3 VDD0.8 VVVVVVV (Note 4)(Note 4)(Note 4)(Note 4)(Note 4)SMBus disabled (Note 4)SMBus enabled (Note 4)
DI20 VIH Input High VoltageI/O pins:with Analog FunctionsDigital Onlywith TTL Bufferwith Schmitt Trigger BufferMCLROSC1 (XT mode)OSC1 (HS mode)SDAx, SCLxSDAx, SCLx 0.8 VDD0.8 VDD0.25VDD + 0.8V0.8 VDD0.8 VDD0.7 VDD0.7 VDD0.7 VDD2.1 ————————— VDDVDD5.55.5VDDVDDVDD5.55.5 VVVVVVVVV (Note 4)(Note 4)(Note 4)(Note 4)(Note 4)(Note 4)(Note 4)SMBus disabled (Note 4)SMBus enabled, 2.3V ≤ VPIN ≤ 5.5 (Note 4)
DI30 ICNPU CNxx Pull up Current 50 250 400 μA VDD = 3.3V, VPIN = VSS
DI50 IIL Input Leakage CurrentI/O Ports — — ±1 μA (Note 3)VSS ≤ VPIN ≤ VDD,Pin at high-impedance
DI51 Analog Input Pins — — ±1 μA VSS ≤ VPIN ≤ VDD,Pin at high-impedance
DI55 MCLR — — ±1 μA VSS ≤ VPIN ≤ VDD
DI56 OSC1 — — ±1 μA VSS ≤ VPIN ≤ VDD,XT and HS modes

Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
4: This parameter is characterized, but not tested in manufacturing.

TABLE 29-9: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS

DC CHARACTERISTICS

Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +105°C for V-Temp

Param. No. Symbol Characteristics Min. Typical Max. Units Conditions
DO10 VOL Output Low Voltage — — 0.4 V IOL = 7 mA, VDD = 3.6V
I/O Ports — — 0.4 V IOL = 6 mA, VDD = 2.3V
DO16 OSC2/CLKO — — 0.4 V IOL = 3.5 mA, VDD = 3.6V
— — 0.4 V IOL = 2.5 mA, VDD = 2.3V
DO20 VOH Output High Voltage 2.4 — — V IOH = -12 mA, VDD = 3.6V
I/O Ports 1.4 — — V IOH = -12 mA, VDD = 2.3V
DO26 OSC2/CLKO 2.4 — — V IOH = -12 mA, VDD = 3.6V
1.4 — — V IOH = -12 mA, VDD = 2.3V

TABLE 29-10: ELECTRICAL CHARACTERISTICS: BROWN-OUT RESET (BOR)

DC CHARACTERISTICS

Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +105°C for V-Temp

Param. No. Symbol Characteristics Min. Typical Max. Units Conditions
BO10 VBOR BOR Event on VDD transition high-to-low 2.0 — 2.3 V —

TABLE 29-11: DC CHARACTERISTICS: PROGRAM MEMORY(3)

DC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-Temp
Param. No. Symbol Characteristics Min. Typical(1) Max. Units Conditions
D130 EP Program Flash Memory Cell Endurance 1000 — — E/W —
D131 VPR VDD for Read VMIN — 3.6 V —
D132 VPEW VDD for Erase or Write 3.0 — 3.6 V —
D134 TRETD Characteristic Retention 20 — — Year —
D135 IDDP Supply Current during Programming — 10 — mA —
D136 TWW Word Write Cycle Time 20 — 40 μs —
TRW Row Write Cycle Time(2) (128 words per row) 3 4.5 — ms —
D137 TPE Page Erase Cycle Time 20 — — ms —
TCE Chip Erase Cycle Time 80 — — ms —
D138 LVDstartup Flash LVD Delay — — 6 μs —

Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated.
2: The minimum SYSCLK for row programming is 4 MHz. Care should be taken to minimize bus activities during row programming, such as suspending any memory-to-memory DMA operations. If heavy bus loads are expected, selecting Bus Matrix Arbitration mode 2 (rotating priority) may be necessary. The default Arbitration mode is mode 1 (CPU has lowest priority).
3: Refer to the “PIC32MX Flash Programming Specification” (DS61145) for operating conditions during programming and erase cycles.

TABLE 29-12: PROGRAM FLASH MEMORY WAIT STATE CHARACTERISTICS

DC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-Temp
Required Flash wait states SYSCLK Units Comments
0 Wait State 0 to 30 MHz —
1 Wait State 31 to 60
2 Wait States 61 to 80

Note 1: 40 MHz maximum for PIC32MX320F032H and PIC32MX420F032H devices.

TABLE 29-13: COMPARATOR SPECIFICATIONS

DC CHARACTERISTICS

Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +105°C for V-Temp

Param. No. Symbol Characteristics Min. Typical Max. Units Comments
D300 VIOFF Input Offset Voltage — ±7.5 ±25 mV AVDD = VDD, AVSS = VSS
D301 VICM Input Common Mode Voltage 0 — VDD V AVDD = VDD, AVSS = VSS (Note 2)
D302 CMRR Common Mode Rejection Ratio 55 — — dB Max VICM = (VDD - 1)V (Note 2)
D303 TRESP Response Time — 150 400 ns AVDD = VDD, AVSS = VSS (Notes 1,2)
D304 ON2OV Comparator Enabled to Output Valid — — 10 μs Comparator module is configured before setting the comparator ON bit. (Note 2)
D305 IVREF Internal Voltage Reference 0.57 0.6 0.63 V —

Note 1: Response time measured with one comparator input at (VDD – 1.5)/2, while the other input transitions from VSS to VDD.
2: These parameters are characterized but not tested.

TABLE 29-14: VOLTAGE REFERENCE SPECIFICATIONS

DC CHARACTERISTICS

Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +105°C for V-Temp

Param. No. Symbol Characteristics Min. Typical Max. Units Comments
D310 VRES Resolution VDD/24 — VDD/32 LSb —
D311 VRAA Absolute Accuracy — — 1/2 LSb —
D312 TSET Settling Time(1) — — 10 μs —

Note 1: Settling time measured while CVRR = 1 and CVR3:CVR0 transitions from ‘0000’ to ‘1111’. This parameter is characterized, but not tested in manufacturing.

TABLE 29-15: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS

DC CHARACTERISTICS

Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +105°C for V-Temp

Param. No. Symbol Characteristics Min. Typical Max. Units Comments
D320 VCORE Regulator Output Voltage 1.62 1.80 1.98 V —
D321 CEFC External Filter Capacitor Value 8 10 — μF Capacitor must be low series resistance (< 1 Ohm)
D322 TPWRT Power-up Timer Period — 64 — ms ENVREG = 0

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