Microchip PIC32 datasheet: 5.0 Flash program memory

5.0 FLASH PROGRAM MEMORY

Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 5. “Flash Program Memory” (DS61121) of the PIC32 Family Reference Manual, which is available from the Microchip web site (www.microchip.com/PIC32).

2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information.

PIC32MX3XX/4XX devices contain an internal program Flash memory for executing user code. There are three methods by which the user can program this memory:

• Run-Time Self Programming (RTSP) • In-Circuit Serial Programming™ (ICSP™) • EJTAG Programming

EXAMPLE 5-1:

NVMCON = 0x4004; // Enable and configure for erase operation Wait(delay); // Delay for 6 µs for LVDstartup

NVMKEY = 0xAA996655; NVMKEY = 0x556699AA; NVMCONSET = 0x8000; // Initiate operation

while(NVMCONbits.WR==1); // Wait for current operation to complete

RTSP is performed by software executing from either Flash or RAM memory. EJTAG is performed using the EJTAG port of the device and a EJTAG capable programmer. ICSP is performed using a serial data connection to the device and allows much faster programming times than RTSP. RTSP techniques are described in this chapter. The ICSP and EJTAG methods are described in the "PIC32MX Flash Programming Specification" (DS61145), which can be downloaded from the Microchip web site.

Note: Flash LVD Delay (LVDstartup) must be taken into account between setting up and executing any Flash command operation. See Example 5-1 for a code example to set up and execute a Flash command operation.

NOTES:

6.0 RESETS

Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 7. “Resets” (DS61118) of the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).

2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information.

The Reset module combines all Reset sources and controls the device Master Reset signal, SYSRST. The following is a list of device Reset sources:

• POR: Power-on Reset
• \overlineMCLR: Master Clear Reset Pin
• SWR: Software Reset
• WDTR: Watchdog Timer Reset
• BOR: Brown-out Reset
• CMR: Configuration Mismatch Reset

A simplified block diagram of the Reset module is illustrated in Figure 6-1.

FIGURE 6-1: SYSTEM RESET BLOCK DIAGRAM

NOTES:

DS61143H-page 88 © 2011 Microchip Technology Inc.

7.0 INTERRUPT CONTROLLER

Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 8. “Interrupt Controller” (DS61108) of the PIC32 Family Reference Manual, which is available from the Microchip web site (www.microchip.com/PIC32).

2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information.

PIC32MX3XX/4XX devices generate interrupt requests in response to interrupt events from peripheral modules. The Interrupt Control module exists externally to the CPU logic and prioritizes the interrupt events before presenting them to the CPU.

The PIC32MX3XX/4XX interrupts module includes the following features:

• Up to 96 interrupt sources
• Up to 64 interrupt vectors
• Single and Multi-Vector mode operations
• Five external interrupts with edge polarity control
• Interrupt proximity timer
• Module Freeze in Debug mode
• Seven user-selectable priority levels for each vector
• Four user-selectable subpriority levels within each priority
• Dedicated shadow set for highest priority level
• Software can generate any interrupt
• User-configurable interrupt vector table location
• User-configurable interrupt vector spacing

FIGURE 7-1: INTERRUPT CONTROLLER MODULE

Note: Several of the registers cited in this section are not in the interrupt controller module. These registers (and bits) are associated with the CPU. Details about them are available in Section 3.0 “CPU”.

To avoid confusion, a typographic distinction is made for registers in the CPU. The register names in this section, and all other sections of this manual, are signified by uppercase letters only. The CPU register names are signified by upper and lowercase letters. For example, INTSTAT is an Interrupts register; whereas, IntCtl is a CPU register.

TABLE 7-1: INTERRUPT IRQ AND VECTOR LOCATION

Note 1: Not all interrupt sources are available on all devices. See TABLE 1: “PIC32MX General Purpose – Features” and TABLE 2: “PIC32MX USB – Features” for available peripherals.

TABLE 7-1: INTERRUPT IRQ AND VECTOR LOCATION (CONTINUED)

Note 1: Not all interrupt sources are available on all devices. See TABLE 1: “PIC32MX General Purpose – Features” and TABLE 2: “PIC32MX USB – Features” for available peripherals.

NOTES:

8.0 OSCILLATOR CONFIGURATION

Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the "PIC32 Family Reference Manual" Section 6. "Oscillator Configuration" (DS61112), which is available from the Microchip web site (www.microchip.com/PIC32).

2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information.

The PIC32MX oscillator system has the following modules and features:

• A total of four external and internal oscillator options as clock sources
• On-chip PLL (phase-locked loop) with user-selectable input divider, multiplier and output divider to boost operating frequency on select internal and external oscillator sources
• On-chip user-selectable divisor postscaler on select oscillator sources
• Software-controllable switching between various clock sources
• A Fail-Safe Clock Monitor (FSCM) that detects clock failure and permits safe application recovery or shut down
• Dedicated on-chip PLL for USB peripheral

FIGURE 8-1: PIC32MX3XX/4XX FAMILY CLOCK DIAGRAM

Notes:

1. A series resistor, Rs, may be required for AT strip-cut crystals.
2. The internal feedback resistor, Rf, is typically in the range of 2 to 10 MΩ.
3. Refer to the "PIC32 Family Reference Manual" Section 6. "Oscillator Configuration" (DS61112) for help determining the best oscillator components.
4. PBCLK out is available on the OSC2 pin in certain clock modes.

NOTES:

9.0 PREFETCH CACHE

Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 4. “Prefetch Cache” (DS61119) of the PIC32 Family Reference Manual, which is available from the Microchip web site (www.microchip.com/PIC32).

2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information.

Prefetch cache increases performance for applications executing out of the cacheable program Flash memory regions by implementing instruction caching, constant data caching and instruction prefetching.

9.1 Features

• 16 Fully Associative Lockable Cache Lines
• 16-byte Cache Lines
• Up to four Cache Lines Allocated to Data
• Two Cache Lines with Address Mask to hold repeated instructions
• Pseudo LRU replacement policy
• All Cache Lines are software writable
• 16-byte parallel memory fetch
• Predictive Instruction Prefetch

FIGURE 9-1: PREFETCH MODULE BLOCK DIAGRAM

NOTES:

10.0 DIRECT MEMORY ACCESS (DMA) CONTROLLER

Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 31. “Direct Memory Access (DMA) Controller” (DS61117) of the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).

2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information.

The PIC32MX Direct Memory Access (DMA) controller is a bus master module useful for data transfers between different devices without CPU intervention. The source and destination of a DMA transfer can be any of the memory mapped modules existent in the PIC32MX (such as Peripheral Bus (PBUS) devices: SPI, UART, PMP, and so on) or memory itself.

Following are some of the key features of the DMA controller module:

• Four Identical Channels, each featuring:
  • Auto-Increment Source and Destination Address Registers
  • Source and Destination Pointers
  • Memory to Memory and Memory to Peripheral Transfers
• Automatic Word-Size Detection:
  • Transfer Granularity, down to byte level
  • Bytes need not be word-aligned at source and destination
• Fixed Priority Channel Arbitration
• Flexible DMA Channel Operating Modes:
  • Manual (software) or automatic (interrupt) DMA requests
  • One-Shot or Auto-Repeat Block Transfer modes
  • Channel-to-channel chaining
• Flexible DMA Requests:
  • A DMA request can be selected from any of the peripheral interrupt sources
  • Each channel can select any (appropriate) observable interrupt as its DMA request source
  • A DMA transfer abort can be selected from any of the peripheral interrupt sources
  • Pattern (data) match transfer termination
• Multiple DMA Channel Status Interrupts:
  • DMA channel block transfer complete
  • Source empty or half empty
  • Destination full or half-full
  • DMA transfer aborted due to an external event
  • Invalid DMA address generated
• DMA Debug Support Features:
  • Most recent address accessed by a DMA channel
  • Most recent DMA channel to transfer data
• CRC Generation Module:
  • CRC module can be assigned to any of the available channels
  • CRC module is highly configurable

FIGURE 10-1: DMA BLOCK DIAGRAM

NOTES:

DS61143H-page 98 © 2011 Microchip Technology Inc.

11.0 USB ON-THE-GO (OTG)

Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 27. “USB On-The-Go (OTG)” (DS61126) of the PIC32 Family Reference Manual, which is available from the Microchip web site (www.microchip.com/PIC32).

2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information.

The Universal Serial Bus (USB) module contains analog and digital components to provide a USB 2.0 full-speed and low-speed embedded host, full-speed device, or OTG implementation with a minimum of external components. This module in Host mode is intended for use as an embedded host and therefore does not implement a UHCI or OHCI controller.

The USB module consists of the clock generator, the USB voltage comparators, the transceiver, the Serial Interface Engine (SIE), a dedicated USB DMA controller, pull-up and pull-down resistors, and the register interface. A block diagram of the PIC32MX USB OTG module is presented in Figure 11-1.

The clock generator provides the 48 MHz clock required for USB full-speed and low-speed communication. The voltage comparators monitor the voltage on the VBUS pin to determine the state of the bus. The transceiver provides the analog translation between the USB bus and the digital logic. The SIE is a state machine that transfers data to and from the endpoint buffers, and generates the hardware protocol for data transfers. The USB DMA controller transfers data between the data buffers in RAM and the SIE. The integrated pull-up and pull-down resistors eliminate the need for external signaling components. The register interface allows the CPU to configure and communicate with the module.

The PIC32MX USB module includes the following features:

• USB Full-Speed Support for Host and Device
• Low-Speed Host Support
• USB OTG Support
• Integrated Signaling Resistors
• Integrated Analog Comparators for VBUS Monitoring
• Integrated USB Transceiver
• Transaction Handshaking Performed by Hardware
• Endpoint Buffering Anywhere in System RAM
• Integrated DMA to Access System RAM and Flash

Note: The implementation and use of the USB specifications, as well as other third-party specifications or technologies, may require licensing; including, but not limited to, USB Implementers Forum, Inc. (also referred to as USB-IF). The user is fully responsible for investigating and satisfying any applicable licensing obligations.

FIGURE 11-1: PIC32MX3XX/4XX FAMILY USB INTERFACE DIAGRAM

Note 1: PB clock is only available on this pin for select EC modes. 2: Pins can be used as digital inputs when USB is not enabled. 3: This bit field is contained in the OSCCON register. 4: This bit field is contained in the OSCTRM register. 5: USB PLL UFIN requirements: 4 MHz. 6: This bit field is contained in the DEVCFG2 register. 7: A 48 MHz clock is required for proper USB operation. 8: Pins can be used as GPIO when the USB module is disabled.