29.2 AC Characteristics and Timing Parameters
The information contained in this section defines PIC32MX3XX/4XX AC characteristics and timing parameters.
FIGURE 29-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
| Load Condition 1 – for all pins except OSC2 | Load Condition 2 – for OSC2 |
|---|---|
| RL = 464ΩCL = 50 pF for all pins50 pF for OSC2 pin (EC mode) |
TABLE 29-16: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS
| AC CHARACTERISTICS | Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated)Operating temperature -40°C ≤TA ≤+85°C for Industrial-40°C ≤TA ≤+105°C for V-Temp | ||||||
|---|---|---|---|---|---|---|---|
| Param. No. | Symbol | Characteristics | Min. | Typical(1) | Max. | Units | Conditions |
| DO56 | CIO | All I/O pins and OSC2 | — | — | 50 | pF | EC mode |
| DO58 | CB | SCLx, SDAx | — | — | 400 | pF | In I²C™ mode |
Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested.
FIGURE 29-2: EXTERNAL CLOCK TIMING


TABLE 29-17: EXTERNAL CLOCK TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +105°C for V-Temp
| Param. No. | Symbol | Characteristics | Min. | Typical(1) | Max. | Units | Conditions |
|---|---|---|---|---|---|---|---|
| OS10 | FOSC | External CLKI Frequency (External clocks allowed only in EC and ECPLL modes) | DC 4 | — | 50(3) 50(5) | MHz MHz | EC (Note 5) ECPLL (Note 4) |
| OS11 | Oscillator Crystal Frequency | 3 | — | 10 | MHz | XT (Note 5) | |
| OS12 | 4 | — | 10 | MHz | XTPLL (Notes 4, 5) | ||
| OS13 | 10 | — | 25 | MHz | HS (Note 5) | ||
| OS14 | 10 | — | 25 | MHz | HSPLL (Notes 4, 5) | ||
| OS15 | 32 | 32.768 | 100 | kHz | SOSC (Note 5) | ||
| OS20 | TOSC | TOSC = 1/FOSC = TCY(2) | — | — | — | — | See parameter OS10 for FOSC value |
| OS30 | TosL, TosH | External Clock In (OSC1) High or Low Time | 0.45 x TOSC | — | — | ns | EC (Note 5) |
| OS31 | TosR, TosF | External Clock In (OSC1) Rise or Fall Time | — | — | 0.05 x TOSC | ns | EC (Note 5) |
| OS40 | TOST | Oscillator Start-up Timer Period (Only applies to HS, HSPLL, XT, XTPLL and SOSC Clock Oscillator modes) | — | 1024 | — | TOSC | (Note 5) |
| OS41 | TFSCM | Primary Clock Fail Safe Time-out Period | — | 2 | — | ms | (Note 5) |
| OS42 | GM | External Oscillator Transconductance | — | 12 | — | mA/V | VDD = 3.3V TA = +25°C (Note 5) |
Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are characterized but are not tested.
2: Instruction cycle period (TCY) equals the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min.” values with an external clock applied to the OSC1/CLKI pin.
3: 40 MHz maximum for PIC32MX320F032H and PIC32MX420F032H devices.
4: PLL input requirements: 4 MHz ≤ FPLLIN ≤ 5 MHz (use PLL prescaler to reduce FOSC). This parameter is characterized, but tested at 10 MHz only at manufacturing.
5: This parameter is characterized, but not tested in manufacturing.
TABLE 29-18: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.3V TO 3.6V)
| AC CHARACTERISTICS | Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-Temp | ||||||
|---|---|---|---|---|---|---|---|
| Param. No. | Symbol | Characteristics(1) | Min. | Typical | Max. | Units | Conditions |
| OS50 | FPLLI | PLL Voltage Controlled Oscillator (VCO) Input Frequency Range | 4 | — | 5 | MHz | ECPLL, HSPLL, XTPLL, FRCPLL modes |
| OS51 | FSYS | On-Chip VCO System Frequency | 60 | — | 120 | MHz | — |
| OS52 | TLOCK | PLL Start-up Time (Lock Time) | — | — | 2 | ms | — |
| OS53 | DCLK | CLKO Stability(2) (Period Jitter or Cumulative) | -0.25 | — | +0.25 | % | Measured over 100 ms period |
Note 1: These parameters are characterized, but not tested in manufacturing.
2: This jitter specification is based on clock-cycle by clock-cycle measurements. To get the effective jitter for individual time-bases on communication clocks, use the following formula:
$$ EffectiveJitter = \frac{D_{CLK}}{\sqrt{\frac{SYSCLK}{CommunicationClock}}} $$
For example, if SYSCLK = 80 MHz and SPI bit rate = 20 MHz, the effective jitter is as follows:
$$ EffectiveJitter = \frac{D_{CLK}}{\sqrt{\frac{80}{20}}} = \frac{D_{CLK}}{2} $$
TABLE 29-19: INTERNAL FRC ACCURACY
| AC CHARACTERISTICS | Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-Temp | |||||
|---|---|---|---|---|---|---|
| Param. No. | Characteristics | Min. | Typical | Max. | Units | Conditions |
| Internal FRC Accuracy @ 8.00 MHz(1) | ||||||
| F20 | FRC | -2 | — | +2 | % | — |
Note 1: Frequency calibrated at 25°C and 3.3V. TUN bits can be used to compensate for temperature drift.
TABLE 29-20: INTERNAL RC ACCURACY
| AC CHARACTERISTICS | Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-Temp | |||||
|---|---|---|---|---|---|---|
| Param. No. | Characteristics | Min. | Typical | Max. | Units | Conditions |
| LPRC @ 31.25 kHz(1) | ||||||
| F21 | LPRC | -15 | — | +15 | % | — |
Note 1: Change of LPRC frequency as VDD changes.
FIGURE 29-3: I/O TIMING CHARACTERISTICS

Note: Refer to Figure 29-1 for load conditions.
TABLE 29-21: I/O TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +105°C for V-Temp
| Param. No. | Symbol | Characteristics(2) | Min. | Typical(1) | Max. | Units | Conditions |
|---|---|---|---|---|---|---|---|
| DO31 | TioR | Port Output Rise Time | — | 5 | 15 | ns | VDD < 2.5V |
| — | 5 | 10 | ns | VDD > 2.5V | |||
| DO32 | TioF | Port Output Fall Time | — | 5 | 15 | ns | VDD < 2.5V |
| — | 5 | 10 | ns | VDD > 2.5V | |||
| DI35 | TINP | INTx Pin High or Low Time | 10 | — | — | ns | — |
| DI40 | TRBP | CNx High or Low Time (input) | 2 | — | — | TSYSCLK | — |
Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated.
2: This parameter is characterized, but not tested in manufacturing.
FIGURE 29-4: POWER-ON RESET TIMING CHARACTERISTICS
Internal Voltage Regulator Enabled Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC)

Internal Voltage Regulator Enabled Clock Sources = (HS, HSPLL, XT, XTPLL and Sosc)
External VCORE Provided Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC)
Note 1: The Power-up period will be extended if the power-up sequence completes before the device exits from BOR ($V_{DD} < V_{DDMIN}$). 2: Includes interval voltage regulator stabilization delay. 3: Power-up Timer (PWRT); only active when the internal voltage regulator is disabled.
FIGURE 29-5: EXTERNAL RESET TIMING CHARACTERISTICS
Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC)

Clock Sources = (HS, HSPLL, XT, XTPLL and Sosc)
TABLE 29-22: RESETS TIMING
AC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+105°C for V-Temp
| Param. No. | Symbol | Characteristics(1) | Min. | Typical(2) | Max. | Units | Conditions |
|---|---|---|---|---|---|---|---|
| SY00 | TPU | Power-up Period Internal Voltage Regulator Enabled | — | 400 | 600 | µs | -40°C to +85°C |
| SY01 | TPWRT | Power-up Period External Vcore Applied (Power-Up-Timer Active) | 48 | 64 | 80 | ms | -40°C to +85°C |
| SY02 | TSYSPLY | System Delay Period: Time required to reload Device Configuration Fuses plus SYSCLK delay before first instruction is fetched. | — | 1 µs + 8 SYSCLK cycles | — | — | -40°C to +85°C |
| SY20 | TMCLR | MCLR Pulse Width (low) | — | 2 | — | µs | -40°C to +85°C |
| SY30 | TBOR | BOR Pulse Width (low) | — | 1 | — | µs | -40°C to +85°C |
Note 1: These parameters are characterized, but not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Characterized by design but not tested.
FIGURE 29-6: TIMER1, 2, 3, 4, 5 EXTERNAL CLOCK TIMING CHARACTERISTICS

Note: Refer to Figure 29-1 for load conditions.
TABLE 29-23: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1)
AC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +105°C for V-Temp
| Param. No. | Symbol | Characteristics(2) | Min. | Typical | Max. | Units | Conditions | |
|---|---|---|---|---|---|---|---|---|
| TA10 | TTXH | TxCK High Time | Synchronous, with prescaler | [(12.5 ns or 1TPB)/N] + 25 ns | — | — | ns | Must also meet parameter TA15. |
| Asynchronous, with prescaler | 10 | — | — | ns | — | |||
| TA11 | TTXL | TxCK Low Time | Synchronous, with prescaler | [(12.5 ns or 1TPB)/N] + 25 ns | — | — | ns | Must also meet parameter TA15. |
| Asynchronous, with prescaler | 10 | — | — | ns | — | |||
| TA15 | TTXP | TxCK Input Period | Synchronous, with prescaler | [(Greater of 25 ns or 2TPB)/N] + 30 ns | — | — | ns | VDD > 2.7V |
| [(Greater of 25 ns or 2TPB)/N] + 50 ns | — | — | ns | VDD < 2.7V | ||||
| Asynchronous, with prescaler | 20 | — | — | ns | VDD > 2.7V (Note 3) | |||
| 50 | — | — | ns | VDD < 2.7V (Note 3) | ||||
| OS60 | FT1 | SOSC1/T1CK Oscillator Input Frequency Range (oscillator enabled by setting TCS bit (T1CON<1>)) | 32 | — | 100 | kHz | — | |
| TA20 | TCKEXTMRL | Delay from External TxCK Clock Edge to Timer Increment | — | 1 | TPB | — |
Note 1: Timer1 is a Type A.
Note 2: This parameter is characterized, but not tested in manufacturing.
Note 3: N = prescale value (1, 8, 64, 256)
TABLE 29-24: TIMER2, 3, 4, 5 EXTERNAL CLOCK TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +105°C for V-Temp
| Param. No. | Symbol | Characteristics(1) | Min. | Max. | Units | Conditions | ||
|---|---|---|---|---|---|---|---|---|
| TB10 | TTxH | TxCK High Time | Synchronous, with prescaler | [(12.5 ns or 1TPB)/N] + 25 ns | — | ns | Must also meet parameter TB15. | N = prescale value (1, 2, 4, 8, 16, 32, 64, 256) |
| TB11 | TTxL | TxCK Low Time | Synchronous, with prescaler | [(12.5 ns or 1TPB)/N] + 25 ns | — | ns | Must also meet parameter TB15. | |
| TB15 | TTxP | TxCK Input Period | Synchronous, with prescaler | [(Greater of 25 ns or 2 TPB)/N] + 30 ns | — | ns | VDD > 2.7V | |
| [(Greater of 25 ns or 2 TPB)/N] + 50 ns | — | ns | VDD < 2.7V | — | ||||
| TB20 | TCKEXTMRL | Delay from External TxCK Clock Edge to Timer Increment | — | 1 | TPB | — |
Note 1: These parameters are characterized, but not tested in manufacturing.
FIGURE 29-7: INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS

Note: Refer to Figure 29-1 for load conditions.
TABLE 29-25: INPUT CAPTURE MODULE TIMING REQUIREMENTS
| AC CHARACTERISTICS | Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-Temp | |||||
|---|---|---|---|---|---|---|
| Param. No. | Symbol | Characteristics(1) | Min. | Max. | Units | Conditions |
| IC10 | TccL | ICx Input Low Time | [(12.5 ns or 1TPB)/N] + 25 ns | — | ns | Must also meet parameter IC15. N = prescale value (1, 4, 16) |
| IC11 | TccH | ICx Input High Time | [(12.5 ns or 1TPB)/N] + 25 ns | — | ns | Must also meet parameter IC15. |
| IC15 | TccP | ICx Input Period | [(25 ns or 2TPB)/N] + 50 ns | — | ns | — |
Note 1: These parameters are characterized, but not tested in manufacturing.
FIGURE 29-8: OUTPUT COMPARE MODULE (OCx) TIMING CHARACTERISTICS

Note: Refer to Figure 29-1 for load conditions.
TABLE 29-26: OUTPUT COMPARE MODULE TIMING REQUIREMENTS
| AC CHARACTERISTICS | Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-Temp | ||||||
|---|---|---|---|---|---|---|---|
| Param. No. | Symbol | Characteristics(1) | Min. | Typical(2) | Max. | Units | Conditions |
| OC10 | TccF | OCx Output Fall Time | — | — | — | ns | See parameter DO32. |
| OC11 | TccR | OCx Output Rise Time | — | — | — | ns | See parameter DO31. |
Note 1: These parameters are characterized, but not tested in manufacturing.
Note 2: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested.
FIGURE 29-9: OC/PWM MODULE TIMING CHARACTERISTICS

Note: Refer to Figure 29-1 for load conditions.
TABLE 29-27: SIMPLE OC/PWM MODE TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +105°C for V-Temp
| Param No. | Symbol | Characteristics(1) | Min | Typical(2) | Max | Units | Conditions |
|---|---|---|---|---|---|---|---|
| OC15 | TFD | Fault Input to PWM I/O Change | — | — | 25 | ns | — |
| OC20 | TFLT | Fault Input Pulse Width | 50 | — | — | ns | — |
Note 1: These parameters are characterized, but not tested in manufacturing.
Note 2: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested.
FIGURE 29-10: SPIx MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS

Note: Refer to Figure 29-1 for load conditions.
TABLE 29-28: SPIx MASTER MODE (CKE = 0) TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+105°C for V-Temp
| Param. No. | Symbol | Characteristics(1) | Min. | Typical(2) | Max. | Units | Conditions |
|---|---|---|---|---|---|---|---|
| SP10 | TsCL | SCKx Output Low Time(3) | Tsck/2 | — | — | ns | — |
| SP11 | TsCH | SCKx Output High Time(3) | Tsck/2 | — | — | ns | — |
| SP20 | TsCF | SCKx Output Fall Time(4) | — | — | — | ns | See parameter DO32 |
| SP21 | TsCR | SCKx Output Rise Time(4) | — | — | — | ns | See parameter DO31 |
| SP30 | TdOF | SDOx Data Output Fall Time(4) | — | — | — | ns | See parameter DO32 |
| SP31 | TdOR | SDOx Data Output Rise Time(4) | — | — | — | ns | See parameter DO31 |
| SP35 | TsCH2dOV, TsCL2dOV | SDOx Data Output Valid after SCKx Edge | — | — | 15 | ns | VDD > 2.7V |
| — | — | 20 | ns | VDD < 2.7V | |||
| SP40 | TdIV2sCH, TdIV2sCL | Setup Time of SDIx Data Input to SCKx Edge | 10 | — | — | ns | — |
| SP41 | TsCH2dIL, TsCL2dIL | Hold Time of SDIx Data Input to SCKx Edge | 10 | — | — | ns | — |
Note 1: These parameters are characterized, but not tested in manufacturing.
2: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested.
3: The minimum clock period for SCKx is 40 ns. Therefore, the clock generated in Master mode must not violate this specification.
4: Assumes 50 pF load on all SPIx pins.
FIGURE 29-11: SPIx MODULE MASTER MODE (CKE = 1) TIMING CHARACTERISTICS

Note: Refer to Figure 29-1 for load conditions.
TABLE 29-29: SPIx MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +105°C for V-Temp
| Param. No. | Symbol | Characteristics(1) | Min. | Typical(2) | Max. | Units | Conditions |
|---|---|---|---|---|---|---|---|
| SP10 | TsCL | SCKx Output Low Time(3) | TsCK/2 | — | — | ns | — |
| SP11 | TsCH | SCKx Output High Time(3) | TsCK/2 | — | — | ns | — |
| SP20 | TsCF | SCKx Output Fall Time(4) | — | — | — | ns | See parameter DO32 |
| SP21 | TsCR | SCKx Output Rise Time(4) | — | — | — | ns | See parameter DO31 |
| SP30 | TdOF | SDOx Data Output Fall Time(4) | — | — | — | ns | See parameter DO32 |
| SP31 | TdOR | SDOx Data Output Rise Time(4) | — | — | — | ns | See parameter DO31 |
| SP35 | TsCH2dOV, TsCL2dOV | SDOx Data Output Valid after SCKx Edge | — | — | 15 | ns | VDD > 2.7V |
| — | — | 20 | ns | VDD < 2.7V | |||
| SP36 | TdOV2sc, TdOV2sCL | SDOx Data Output Setup to First SCKx Edge | 15 | — | — | ns | — |
| SP40 | TdI V2sCH, TdI V2sCL | Setup Time of SDIx Data Input to SCKx Edge | 15 | — | — | ns | VDD > 2.7V |
| 20 | — | — | ns | VDD < 2.7V | |||
| SP41 | TsCH2dIL, TsCL2dIL | Hold Time of SDIx Data Input to SCKx Edge | 15 | — | — | ns | VDD > 2.7V |
| 20 | — | — | ns | VDD < 2.7V |
Note 1: These parameters are characterized, but not tested in manufacturing.
2: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested.
3: The minimum clock period for SCKx is 40 ns. Therefore, the clock generated in Master mode must not violate this specification.
4: Assumes 50 pF load on all SPIx pins.
FIGURE 29-12: SPIx MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS

Note: Refer to Figure 29-1 for load conditions.
TABLE 29-30: SPIx MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +105°C for V-Temp
| Param. No. | Symbol | Characteristics(1) | Min. | Typical(2) | Max. | Units | Conditions |
|---|---|---|---|---|---|---|---|
| SP70 | TsCL | SCKx Input Low Time(3) | TsCK/2 | — | — | ns | — |
| SP71 | TsCH | SCKx Input High Time(3) | TsCK/2 | — | — | ns | — |
| SP72 | TsCF | SCKx Input Fall Time | — | — | — | ns | See parameter DO32 |
| SP73 | TsCR | SCKx Input Rise Time | — | — | — | ns | See parameter DO31 |
| SP30 | TdoF | SDOx Data Output Fall Time(4) | — | — | — | ns | See parameter DO32 |
| SP31 | TdoR | SDOx Data Output Rise Time(4) | — | — | — | ns | See parameter DO31 |
| SP35 | TsCH2doV, TsCL2doV | SDOx Data Output Valid after SCKx Edge | — | — | 15 | ns | VDD > 2.7V |
| — | — | 20 | ns | VDD < 2.7V | |||
| SP40 | TdIV2sCH, TdIV2sCL | Setup Time of SDIx Data Input to SCKx Edge | 10 | — | — | ns | — |
| SP41 | TsCH2dIL, TsCL2dIL | Hold Time of SDIx Data Input to SCKx Edge | 10 | — | — | ns | — |
| SP50 | TssL2sCH, TssL2sCL | SSx ↓ to SCKx ↑ or SCKx Input | 175 | — | — | ns | — |
| SP51 | TssH2doZ | SSx ↑ to SDOx Output High-Impedance(3) | 5 | — | 25 | ns | — |
| SP52 | TsCH2ssH TsCL2ssH | SSx after SCKx Edge | TsCK + 20 | — | — | ns | — |
Note 1: These parameters are characterized, but not tested in manufacturing.
2: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested.
3: The minimum clock period for SCKx is 40 ns.
4: Assumes 50 pF load on all SPIx pins.
FIGURE 29-13: SPIx MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS

Note: Refer to Figure 29-1 for load conditions.
TABLE 29-31: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +105°C for V-Temp
| Param. No. | Symbol | Characteristics(1) | Min. | Typical(2) | Max. | Units | Conditions |
|---|---|---|---|---|---|---|---|
| SP70 | TsCL | SCKx Input Low Time(3) | TsCK/2 | — | — | ns | — |
| SP71 | TsCH | SCKx Input High Time(3) | TsCK/2 | — | — | ns | — |
| SP72 | TsCF | SCKx Input Fall Time | — | 5 | 10 | ns | — |
| SP73 | TsCR | SCKx Input Rise Time | — | 5 | 10 | ns | — |
| SP30 | TdOF | SDOx Data Output Fall Time(4) | — | — | — | ns | See parameter DO32 |
| SP31 | TdOR | SDOx Data Output Rise Time(4) | — | — | — | ns | See parameter DO31 |
| SP35 | TsCH2dOV, TsCL2dOV | SDOx Data Output Valid after SCKx Edge | — | — | 20 | ns | VDD > 2.7V |
| — | — | 30 | ns | VDD < 2.7V | |||
| SP40 | TdI/V2sCH, TdI/V2sCL | Setup Time of SDIx Data Input to SCKx Edge | 10 | — | — | ns | — |
| SP41 | TsCH2dIL, TsCL2dIL | Hold Time of SDIx Data Input to SCKx Edge | 10 | — | — | ns | — |
| SP50 | TssL2sCH, TssL2sCL | SSx ↓ to SCKx ↓ or SCKx ↑ Input | 175 | — | — | ns | — |
| SP51 | TssH2dOZ | SSx ↑ to SDOx Output High-Impedance(4) | 5 | — | 25 | ns | — |
| SP52 | TsCH2ssH TsCL2ssH | SSx ↑ after SCKx Edge | TsCK + 20 | — | — | ns | — |
| SP60 | TssL2dOV | SDOx Data Output Valid after SSx Edge | — | — | 25 | ns | — |
Note 1: These parameters are characterized, but not tested in manufacturing.
Note 2: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested.
Note 3: The minimum clock period for SCKx is 40 ns.
Note 4: Assumes 50 pF load on all SPIx pins.
FIGURE 29-14: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE)

Note: Refer to Figure 29-1 for load conditions.
FIGURE 29-15: I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE)

Note: Refer to Figure 29-1 for load conditions.
TABLE 29-32: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE)
AC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +105°C for V-Temp
| Param. No. | Symbol | Characteristics | Min.(1) | Max. | Units | Conditions | |
|---|---|---|---|---|---|---|---|
| IM10 | TLO:SCL | Clock Low Time | 100 kHz mode | TPB * (BRG + 2) | — | µs | — |
| 400 kHz mode | TPB * (BRG + 2) | — | µs | ||||
| 1 MHz mode(2) | TPB * (BRG + 2) | — | µs | ||||
| IM11 | THI:SCL | Clock High Time | 100 kHz mode | TPB * (BRG + 2) | — | µs | — |
| 400 kHz mode | TPB * (BRG + 2) | — | µs | ||||
| 1 MHz mode(2) | TPB * (BRG + 2) | — | µs | ||||
| IM20 | TF:SCL | SDAx and SCLx Fall Time | 100 kHz mode | — | 300 | ns | CB is specified to be from 10 to 400 pF. |
| 400 kHz mode | 20 + 0.1 CB | 300 | ns | ||||
| 1 MHz mode(2) | — | 100 | ns | ||||
| IM21 | TR:SCL | SDAx and SCLx Rise Time | 100 kHz mode | — | 1000 | ns | CB is specified to be from 10 to 400 pF. |
| 400 kHz mode | 20 + 0.1 CB | 300 | ns | ||||
| 1 MHz mode(2) | — | 300 | ns | ||||
| IM25 | TSU:DAT | Data Input Setup Time | 100 kHz mode | 250 | — | ns | — |
| 400 kHz mode | 100 | — | ns | ||||
| 1 MHz mode(2) | 100 | — | ns | ||||
| IM26 | THD:DAT | Data Input Hold Time | 100 kHz mode | 0 | — | µs | — |
| 400 kHz mode | 0 | 0.9 | µs | ||||
| 1 MHz mode(2) | 0 | 0.3 | µs | ||||
| IM30 | TSU:STA | Start Condition Setup Time | 100 kHz mode | TPB * (BRG + 2) | — | µs | Only relevant for Repeated Start condition. |
| 400 kHz mode | TPB * (BRG + 2) | — | µs | ||||
| 1 MHz mode(2) | TPB * (BRG + 2) | — | µs | ||||
| IM31 | THD:STA | Start Condition Hold Time | 100 kHz mode | TPB * (BRG + 2) | — | µs | After this period, the first clock pulse is generated. |
| 400 kHz mode | TPB * (BRG + 2) | — | µs | ||||
| 1 MHz mode(2) | TPB * (BRG + 2) | — | µs | ||||
| IM33 | TSU:STO | Stop Condition Setup Time | 100 kHz mode | TPB * (BRG + 2) | — | µs | — |
| 400 kHz mode | TPB * (BRG + 2) | — | µs | ||||
| 1 MHz mode(2) | TPB * (BRG + 2) | — | µs | ||||
| IM34 | THD:STO | Stop Condition Hold Time | 100 kHz mode | TPB * (BRG + 2) | — | ns | — |
| 400 kHz mode | TPB * (BRG + 2) | — | ns | ||||
| 1 MHz mode(2) | TPB * (BRG + 2) | — | ns | ||||
| IM40 | TAA:SCL | Output Valid from Clock | 100 kHz mode | — | 3500 | ns | — |
| 400 kHz mode | — | 1000 | ns | ||||
| 1 MHz mode(2) | — | 350 | ns | ||||
| IM45 | TBF:SDA | Bus Free Time | 100 kHz mode | 4.7 | — | µs | The amount of time the bus must be free before a new transmission can start. |
| 400 kHz mode | 1.3 | — | µs | ||||
| 1 MHz mode(2) | 0.5 | — | µs | ||||
| IM50 | CB | Bus Capacitive Loading | — | 400 | pF | — | |
| IM51 | TPGD | Pulse Gobbler Delay(3) | 52 | 312 | ns | — |
Note 1: BRG is the value of the I²C™ Baud Rate Generator.
2: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
3: The typical value for this parameter is 104 ns.
FIGURE 29-16: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE)

Note: Refer to Figure 29-1 for load conditions.
FIGURE 29-17: I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE)

Note: Refer to Figure 29-1 for load conditions.
TABLE 29-33: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE)
AC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+105°C for V-Temp
| Param. No. | Symbol | Characteristics | Min. | Max. | Units | Conditions | |
|---|---|---|---|---|---|---|---|
| IS10 | TLO:SCL | Clock Low Time | 100 kHz mode | 4.7 | — | µs | PBCLK must operate at a minimum of 800 KHz. |
| 400 kHz mode | 1.3 | — | µs | PBCLK must operate at a minimum of 3.2 MHz. | |||
| 1 MHz mode(1) | 0.5 | — | µs | — | |||
| IS11 | THI:SCL | Clock High Time | 100 kHz mode | 4.0 | — | µs | PBCLK must operate at a minimum of 800 KHz. |
| 400 kHz mode | 0.6 | — | µs | PBCLK must operate at a minimum of 3.2 MHz. | |||
| 1 MHz mode(1) | 0.5 | — | µs | — | |||
| IS20 | TF:SCL | SDAx and SCLx Fall Time | 100 kHz mode | — | 300 | ns | CB is specified to be from 10 to 400 pF. |
| 400 kHz mode | 20 + 0.1 CB | 300 | ns | ||||
| 1 MHz mode(1) | — | 100 | ns | ||||
| IS21 | TR:SCL | SDAx and SCLx Rise Time | 100 kHz mode | — | 1000 | ns | CB is specified to be from 10 to 400 pF. |
| 400 kHz mode | 20 + 0.1 CB | 300 | ns | ||||
| 1 MHz mode(1) | — | 300 | ns | ||||
| IS25 | TSU:DAT | Data Input Setup Time | 100 kHz mode | 250 | — | ns | — |
| 400 kHz mode | 100 | — | ns | ||||
| 1 MHz mode(1) | 100 | — | ns | ||||
| IS26 | THD:DAT | Data Input Hold Time | 100 kHz mode | 0 | — | ns | — |
| 400 kHz mode | 0 | 0.9 | µs | ||||
| 1 MHz mode(1) | 0 | 0.3 | µs | ||||
| IS30 | TSU:STA | Start Condition Setup Time | 100 kHz mode | 4700 | — | ns | Only relevant for Repeated Start condition. |
| 400 kHz mode | 600 | — | ns | ||||
| 1 MHz mode(1) | 250 | — | ns | ||||
| IS31 | THD:STA | Start Condition Hold Time | 100 kHz mode | 4000 | — | ns | After this period, the first clock pulse is generated. |
| 400 kHz mode | 600 | — | ns | ||||
| 1 MHz mode(1) | 250 | — | ns | ||||
| IS33 | TSU:STO | Stop Condition Setup Time | 100 kHz mode | 4000 | — | ns | — |
| 400 kHz mode | 600 | — | ns | ||||
| 1 MHz mode(1) | 600 | — | ns | ||||
| IS34 | THD:STO | Stop Condition Hold Time | 100 kHz mode | 4000 | — | ns | — |
| 400 kHz mode | 600 | — | ns | ||||
| 1 MHz mode(1) | 250 | — | ns | ||||
| IS40 | TAA:SCL | Output Valid from Clock | 100 kHz mode | 0 | 3500 | ns | — |
| 400 kHz mode | 0 | 1000 | ns | ||||
| 1 MHz mode(1) | 0 | 350 | ns | ||||
| IS45 | TBF:SDA | Bus Free Time | 100 kHz mode | 4.7 | — | µs | The amount of time the bus must be free before a new transmission can start. |
| 400 kHz mode | 1.3 | — | µs | ||||
| 1 MHz mode(1) | 0.5 | — | µs | ||||
| IS50 | CB | Bus Capacitive Loading | — | 400 | pF | — |
Note 1: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
DS61143H-page 178 © 2011 Microchip Technology Inc.
TABLE 29-34: ADC MODULE SPECIFICATIONS
AC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +105°C for V-Temp
| Param. No. | Symbol | Characteristics | Min. | Typical | Max. | Units | Conditions |
|---|---|---|---|---|---|---|---|
| Device Supply | |||||||
| AD01 | AVDD | Module VDD Supply | Greater of VDD – 0.3 or 2.5 | — | Lesser of VDD + 0.3 or 3.6 | V | — |
| AD02 | AVSS | Module Vss Supply | Vss | — | Vss + 0.3 | V | — |
| Reference Inputs | |||||||
| AD05 | VREFH | Reference Voltage High | AVss + 2.0 | — | AVDD | V | (Note 1) |
| AD05a | 2.5 | — | 3.6 | V | VREFH = AVDD (Note 3) | ||
| AD06 | VREFL | Reference Voltage Low | AVss | — | VREFH – 2.0 | V | (Note 1) |
| AD07 | VREF | Absolute Reference Voltage (VREFH – VREFL) | 2.0 | — | AVDD | V | (Note 3) |
| AD08 | IREF | Current Drain | — | 250 | 400 | μA | ADC operating |
| — | 3 | μA | ADC off | ||||
| Analog Input | |||||||
| AD12 | VINH-VINL | Full-Scale Input Span | VREFL | — | VREFH | V | — |
| AD13 | VINL | Absolute VINL Input Voltage | AVss – 0.3 | — | AVDD/2 | V | — |
| AD14 | VIN | Absolute Input Voltage | AVss – 0.3 | — | AVDD + 0.3 | V | — |
| AD15 | — | Leakage Current | — | ±0.001 | ±0.610 | μA | VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.3V Source Impedance = 10KΩ |
| AD17 | RIN | Recommended Impedance of Analog Voltage Source | — | — | 5K | Ω | (Note 1) |
| ADC Accuracy – Measurements with External VREF+/VREF- | |||||||
| AD20c | Nr | Resolution | 10 data bits | bits | — | ||
| AD21c | INL | Integral Nonlinearity | — | — | <±1 | LSb | VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.3V |
| AD22c | DNL | Differential Nonlinearity | — | — | <±1 | LSb | VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.3V (Note 2) |
| AD23c | GERR | Gain Error | — | — | <±1 | LSb | VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.3V |
| AD24n | EOFF | Offset Error | — | — | <±1 | LSb | VINL = AVSS = 0V, AVDD = 3.3V |
| AD25c | — | Monotonicity | — | — | — | — | Guaranteed |
Note 1: These parameters are not characterized or tested in manufacturing.
2: With no missing codes.
3: These parameters are characterized, but not tested in manufacturing.
4: Characterized with 1 kHz sinewave.
TABLE 29-34: ADC MODULE SPECIFICATIONS (CONTINUED)
AC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +105°C for V-Temp
| Param. No. | Symbol | Characteristics | Min. | Typical | Max. | Units | Conditions |
|---|---|---|---|---|---|---|---|
| ADC Accuracy – Measurements with Internal VREF+/VREF- | |||||||
| AD20d | Nr | Resolution | 10 data bits | bits | (Note 3) | ||
| AD21d | INL | Integral Nonlinearity | — | — | <±1 | LSb | VINL = AVSS = 0V, AVDD = 2.5V to 3.6V (Note 3) |
| AD22d | DNL | Differential Nonlinearity | — | — | <±1 | LSb | VINL = AVSS = 0V, AVDD = 2.5V to 3.6V (Notes 2,3) |
| AD23d | GERR | Gain Error | — | — | <±4 | LSb | VINL = AVSS = 0V, AVDD = 2.5V to 3.6V (Note 3) |
| AD24d | EOFF | Offset Error | — | — | <±2 | LSb | VINL = AVSS = 0V, AVDD = 2.5V to 3.6V (Note 3) |
| AD25d | — | Monotonicity | — | — | — | — | Guaranteed |
| Dynamic Performance | |||||||
| AD31b | SINAD | Signal to Noise and Distortion | 55 | 58.5 | — | dB | (Notes 3, 4) |
| AD34b | ENOB | Effective Number of Bits | 9.0 | 9.5 | — | bits | (Notes 3, 4) |
Note 1: These parameters are not characterized or tested in manufacturing.
2: With no missing codes.
3: These parameters are characterized, but not tested in manufacturing.
4: Characterized with 1 kHz sinewave.
TABLE 29-35: 10-BIT ADC CONVERSION RATE PARAMETERS(2)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+105°C for V-Temp
| ADC Speed | TAD Minimum | Sampling Time Min | Rs Max | VDD | ADC Channels Configuration |
|---|---|---|---|---|---|
| 1 MIPS to 400 ksps(1) | 65 ns | 132 ns | 500Ω | 3.0V to 3.6V | |
| Up to 400 ksps | 200 ns | 200 ns | 5.0 kΩ | 2.5V to 3.6V | |
| Up to 300 ksps | 200 ns | 200 ns | 5.0 kΩ | 2.5V to 3.6V |
Note 1: External VREF- and VREF+ pins must be used for correct operation.
2: These parameters are characterized, but not tested in manufacturing.
TABLE 29-36: ANALOG-TO-DIGITAL CONVERSION TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+105°C for V-Temp
| Param. No. | Symbol | Characteristics | Min. | Typical(1) | Max. | Units | Conditions |
|---|---|---|---|---|---|---|---|
| Clock Parameters | |||||||
| AD50 | TAD | Analog-to-Digital Clock Period | 65 | — | — | ns | See Table 29-35 and Note 2 |
| AD51 | TRC | Analog-to-Digital Internal RC Oscillator Period | — | 250 | — | ns | See Note 3 |
| Conversion Rate | |||||||
| AD55 | TCONV | Conversion Time | — | 12 TAD | — | — | — |
| AD56 | FCNV | Throughput Rate (Sampling Speed) | — | — | 1000 | KSPS | AVDD = 3.0V to 3.6V |
| — | — | 400 | KSPS | AVDD = 2.5V to 3.6V | |||
| AD57 | TSAMP | Sample Time | 1 TAD | — | — | — | TSAMP must be ≥ 132 ns. |
| Timing Parameters | |||||||
| AD60 | TPCS | Conversion Start from Sample Trigger | — | 1.0 TAD | — | — | Auto-Convert Trigger (SSRC<2:0> = 111) not selected. See Note 3 |
| AD61 | TPSS | Sample Start from Setting Sample (SAMP) bit | 0.5 TAD | — | 1.5 TAD | — | — |
| AD62 | TCSS | Conversion Completion to Sample Start (ASAM = 1) | — | 0.5 TAD | — | — | See Note 3 |
| AD63 | TDPU | Time to Stabilize Analog Stage from Analog-to-Digital OFF to Analog-to-Digital ON | — | — | 2 | µs | See Note 3 |
Note 1: These parameters are characterized, but not tested in manufacturing.
2: Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity performance, especially at elevated temperatures.
3: Characterized by design but not tested.
FIGURE 29-18: ANALOG-TO-DIGITAL CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (CHPS<1:0> = 01, SIMSAM = 0, ASAM = 0, SSRC<2:0> = 000)

① – Software sets ADxCON. SAMP to start sampling. ② – Sampling starts after discharge period. TSAMP is described in Section 17. “10-bit Analog-to-Digital Converter (ADC)” (DS61104) of the “PIC32 Family Reference Manual”. ③ – Software clears ADxCON. SAMP to start conversion. ④ – Sampling ends, conversion sequence starts. ⑤ – Convert bit 9. ⑥ – Convert bit 8. ⑦ – Convert bit 0. ⑧ – One TAD for end of conversion.
FIGURE 29-19: ANALOG-TO-DIGITAL CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (CHPS<1:0> = 01, SIMSAM = 0, ASAM = 1, SSRC<2:0> = 111, SAMC<4:0> = 00001)

① – Software sets ADxCON. ADON to start AD operation. ② – Sampling starts after discharge period. TSAMP is described in Section 17. “10-bit Analog-to-Digital Converter (ADC)” (DS61104) of the “PIC32 Family Reference Manual”. ③ – Convert bit 9. ④ – Convert bit 8. ⑤ – Convert bit 0. ⑥ – One TAD for end of conversion. ⑦ – Begin conversion of next channel. ⑧ – Sample for time specified by SAMC<4:0>.
DS61143H-page 184 © 2011 Microchip Technology Inc.
FIGURE 29-20: PARALLEL SLAVE PORT TIMING

TABLE 29-37: PARALLEL SLAVE PORT REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+105°C for V-Temp
| Param. No. | Symbol | Characteristics(1) | Min. | Typical | Max. | Units | Conditions |
|---|---|---|---|---|---|---|---|
| PS1 | TdtV2wrH | Data In Valid before WR or CS Inactive (setup time) | 20 | — | — | ns | — |
| PS2 | TwrH2dtl | WR or CS Inactive to Data – In Invalid (hold time) | 40 | — | — | ns | — |
| PS3 | TrdL2dtV | RD and CS Active to Data – Out Valid | — | — | 60 | ns | — |
| PS4 | TrdH2dtl | RD Active or CS Inactive to Data – Out Invalid | 0 | — | 10 | ns | — |
| PS5 | Tcs | CS Active Time | TPB + 40 | — | — | ns | — |
| PS6 | TWR | WR Active Time | TPB + 25 | — | — | ns | — |
| PS7 | TRD | RD Active Time | TPB + 25 | — | — | ns | — |
Note 1: These parameters are characterized, but not tested in manufacturing.
FIGURE 29-21: PARALLEL MASTER PORT READ TIMING DIAGRAM

TABLE 29-38: PARALLEL MASTER PORT READ TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+105°C for V-Temp
| Param. No. | Symbol | Characteristics(1) | Min. | Typical | Max. | Units | Conditions |
|---|---|---|---|---|---|---|---|
| PM1 | TLAT | PMALL/PMALH Pulse Width | — | 1 TPB | — | — | — |
| PM2 | TADSU | Address Out Valid to PMALL/PMALH Invalid (address setup time) | — | 2 TPB | — | — | — |
| PM3 | TADHOLD | PMALL/PMALH Invalid to Address Out Invalid (address hold time) | — | 1 TPB | — | — | — |
| PM4 | TA HOLD | PMRD Inactive to Address Out Invalid (address hold time) | 5 | — | — | ns | — |
| PM5 | TRD | PMRD Pulse Width | — | 1 TPB | — | — | — |
| PM6 | TDSU | PMRD or PMENB Active to Data In Valid (data setup time) | 15 | — | — | ns | — |
| PM7 | TDHOLD | PMRD or PMENB Inactive to Data In Invalid (data hold time) | — | 80 | — | ns | — |
Note 1: These parameters are characterized, but not tested in manufacturing.
FIGURE 29-22: PARALLEL MASTER PORT WRITE TIMING DIAGRAM

TABLE 29-39: PARALLEL MASTER PORT WRITE TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+105°C for V-Temp
| Param. No. | Symbol | Characteristics(1) | Min. | Typical | Max. | Units | Conditions |
|---|---|---|---|---|---|---|---|
| PM11 | TWR | PMWR Pulse Width | — | 1 TPB | — | — | — |
| PM12 | TDVSU | Data Out Valid before PMWR or PMENB goes Inactive (data setup time) | — | 2 TPB | — | — | — |
| PM13 | TDVHOLD | PMWR or PMEMB Invalid to Data Out Invalid (data hold time) | — | 1 TPB | — | — | — |
Note 1: These parameters are characterized, but not tested in manufacturing.
TABLE 29-40: OTG ELECTRICAL SPECIFICATIONS
AC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+105°C for V-Temp
| Param. No. | Symbol | Characteristics(1) | Min. | Typ | Max. | Units | Conditions |
|---|---|---|---|---|---|---|---|
| USB313 | VUSB | USB Voltage | 3.0 | — | 3.6 | V | Voltage on VUSB must be in this range for proper USB operation. |
| USB315 | VILUSB | Input Low Voltage for USB Buffer | — | — | 0.8 | V | — |
| USB316 | VIHUSB | Input High Voltage for USB Buffer | 2.0 | — | — | V | — |
| USB318 | VDIFS | Differential Input Sensitivity | — | — | 0.2 | V | The difference between D+ and D- must exceed this value while VCM is met. |
| USB319 | VCM | Differential Common Mode Range | 0.8 | — | 2.5 | V | — |
| USB320 | ZOUT | Driver Output Impedance | 28.0 | — | 44.0 | Ω | — |
| USB321 | VOL | Voltage Output Low | 0.0 | — | 0.3 | V | 1.5 kΩ load connected to 3.6V. |
| USB322 | VOH | Voltage Output High | 2.8 | — | 3.6 | V | 1.5 kΩ load connected to ground. |
Note 1: These parameters are characterized, but not tested in manufacturing.
FIGURE 29-23: EJTAG TIMING CHARACTERISTICS

TABLE 29-41: EJTAG TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +105°C for V-Temp
| Param. No. | Symbol | Description(1) | Min. | Max. | Units | Conditions |
|---|---|---|---|---|---|---|
| EJ1 | TTCKCYC | TCK Cycle Time | 25 | — | ns | — |
| EJ2 | TTCKHIGH | TCK High Time | 10 | — | ns | — |
| EJ3 | TTCKLOW | TCK Low Time | 10 | — | ns | — |
| EJ4 | TTSETUP | TAP Signals Setup Time Before Rising TCK | 5 | — | ns | — |
| EJ5 | TTHOLD | TAP Signals Hold Time After Rising TCK | 3 | — | ns | — |
| EJ6 | TTDOOUT | TDO Output Delay Time from Falling TCK | — | 5 | ns | — |
| EJ7 | TTDOZSTATE | TDO 3-State Delay Time from Falling TCK | — | 5 | ns | — |
| EJ8 | TTRSTLOW | TRST Low Time | 25 | — | ns | — |
| EJ9 | TRF | TAP Signals Rise/Fall Time, All Input and Output | — | — | ns | — |
Note 1: These parameters are characterized, but not tested in manufacturing.
NOTES:
DS61143H-page 190 © 2011 Microchip Technology Inc.