Want to learn about JTAG

Just so you understand, JTAG is *extremely* device dependent -- that means
chip dependent and, depending on implementation, board dependent.  While it
has signifcant power, it is also very difficult to use properly. Alos it is
not intended for real-time work.

There is no communication "protocol".  There are five wires for JTAG.  One
is a clock.  The other 4 permit reading/writing a serial stream of bits.
Each chip/device has a jtag bit "register" for *EVERY* input and output
between the device and the outside world.  You load and read the registers
by pushing bits around a "loop" of these registers.

There is also a small "command" register that allows you to gate the data
registers for normal signals or jtag bits.  For inputs, the gating causes
the outside world to be ignored and the device sees the bits as if they were
from the outside world.  For outputs, the gating blocks the device outputs
and replaces them with the jtag bits.

The meaning of a serial sequence of bits depends on the particular device
being used, and on the "jtag loop" among devices on the board (assuming
there is more than one jtag device on the board).

I found several hits using google.

An "engineering" view of JTAG can be found at:
  http://www.cs.unc.edu/~msl/PadLibrary/IV.10.pdf
or

http://www.inaccessnetworks.com/projects/ianjtag/jtag-intro/jtag-intro.html
or
  http://www.engr.udayton.edu/faculty/jloomis/ece446/notes/jtag/jtag1.html

The following has Linux/Wine JTAG interface software for the TI XDS510.
  http://www.mit.edu/people/gassend/software/xds510 /

The following site is a "free JTAG tool" for CPLD, a simple logic device.
It includes source code.
  http://www.nahitech.com/nahitafu/naxjp/naxjp-e.html
One drawback -- the main (only?) author is Japanese so the English is a bit
stilted.

Regards,
Steve

It is deterministic, although not terribly fast.



??? Sounds like a protocol to me.



You missed mine, and a number of pages that it references:
   http://recycle.lbl.gov/~ldoolitt/jtag.html
It approaches things from a Linux-centric perspective;
the code given is on-topic for embedded Linux; it's how
I initialize a Xilinx FPGA from a Linux StrongARM.

      - Larry