looking for TTL latch IC

I've posted a new drawing on the same group as your pdf..

I think this is what you are doing.

It still uses 3 IC's like yours. Here the data comes in, passes via 2 tri-state buffers. The Latch clock input is take off a OR gate, so basically when any input pulses high it will pulse the clock input. This assumes however, that the 3state buffer is as slow as they come, since of course, the clock input to the latch needs to pulse slightly faster than the data lines to latch it. The output is ORed to the buffer enable so inputs are off. The buffer also ensures the clock is not pulses again.

Actually, the OR gate with the ABCD inputs could be swapped with resistors, then the delay of the second set of buffers should just be enough to ensure the data is still on the latch when the clock goes low.

Chris

--- The gates on the outputs aren't inverted ORs, they're DeMorgan equivalent ANDs.

The ANDs are HC08's, the ORs are HC32''s, and the latch is an HC175. Upon asserting RESET-, all the true (Q) outputs on the 175 will go low and all the complementary (\Q) outputs will go high. The highs on the complementary outputs will propagate through the ANDS and will enable the clock input of the 175.

If any data inputs (DIN1 - DIN4) are high when RESET is released, the clock input will have already gone high when RESET was asserted and the outputs will remain in their RESET state until ALL the data inputs go low, then ANY of the inputs goes high again. When that happens, the corresponding 175 input will go high and the clock will go high three gate delays later, propagating the inputs which went high prior to one setup time through the 175 to its true outputs and latching them. When any of the 175's true outputs go high its corresponding complementary output will go low, that low will propagate through the ANDs and, three gate delays later, will cause the 175's clock input to go, and stay, low.

If the 175's inputs are low when the 175 comes out of reset, the true outputs will be low, the complementary outputs will be high, and the clock will also be low. In this case, the first high data input will appear on the corresponding 175 input and, three gate delays later, will cause the clock input to go high, clocking that high through the

Data must stay high for three gate delays plus one setup time plus one hold time to be considered valid.

If you need something better/faster, I've posted a new schematic for you on abse. let's move it over there OK?

The ANDs are HC08's, the ORs are HC32's, the flip-flops are HC74's, and you can get all of their AC characteristics by looking at their data sheets.

-- John Fields

That's TWO dinners-for-two at the Rainbow Room, or the Palm Court, or one of each. I prefer the Palm Court myself.

;)

Just copy the address into the browser. OE assumes it's an email address, whereas other readers ask, but can't tell automatically if it's mail or news. I think the OE way is actually better since I click email links much more often. The problem is avoided if the link starts with "news:" to specify that it is a news link.

then

always

D3

do

Right, I will take the newer drawing since that one looks a lot easier to read than the first one. It looks like you have added in a lot of reset function which will of course help over my orig drawing.

The last part of the circuit hasn't been taken into account asyet. This is the part where the outputs are feed back into the inputs. Now assume I link all the Q's together via a 1K resitor and diode back onto the inputs. I will add this onto your drawing for you to see. The last part of the circuit will pull all 4 inputs high (to 12volts not 5v) upon any of the outputs being latched on. I dont think this will effect your design since the inputs should be disabled.

abse is very slow on pipex, I can access text groups fine, though abse takes about 5mins just to DL a message, I will post the edited drawing on there, though it maybe a while before it appears on there.......

thanks Chris

is

onto

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of

ok ABSE it is, you can mail me at tesla@@@@@@@@@@@@@@cps-electronicsREMOVE.co.uk

hopefully you can make sence of that, hopefully the spammers wont ;)

Chris