Funnel shift

Hello Steve,

Next time try Google :-)

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Us HW guys call that a overlap barrel shift (maybe because we like beer...)

Regards, Joerg

I recently used a similar concept, a mux that combines N bits of one register with 16-N bits of another, with programmable N. I call it a "bit blender."

John

+--------------- | snipped-for-privacy@yahoo.com wrote: | >In the course of some tech writing I'm involved in, I've come across | >the term "funnel shift". I get that this has to do with concatenating | >the contents of two registers, or at least part of the contents of two | >registers, into one register. ... ... | I recently used a similar concept, a mux that combines N bits of one | register with 16-N bits of another, with programmable N. I call it a | "bit blender." +---------------

The Am29000 RISC CPU's "EXTRACT" instruction (circa 1984) did precisely this, except for 32 bits instead of 16. The amount of the shift was set in a separate small control register, and EXTRACT specified the two input & one output registers.

You could do a really cool word-at-a-time non-aligned "memcpy()" by setting the shift amount to be the amount of misalignment between the source and destination, then the bulk of the copy being a loop of LOADM (load multiple), a bunch of EXTRACTs to slide the registers down, and a STOREM. If you added a set of unrolled ADDC (add with carry) to that, you could do a non-aligned "memcpy_and_IP_checksum()" in only one clock cycle/byte (asymptotic). [Hey, seemed pretty neat at the time... ;-} ]

-Rob

----- Rob Warnock

627 26th Avenue San Mateo, CA 94403 (650)572-2607

I assume it was mostly used to byte-align data? Arbitrary bit alignment for source packets seems quite unlikely. :-)

That is neat indeed. I still remember how elegant it seemed when I figured out that a combination of six opcodes (one load, one store, one ADC, one adress update (using LEA to avoid flag modification), one loop counter decrement and a JNZ) would combine perfectly on a Pentium:

Three paired opcode bytes resulting in 3 cycles per 4 bytes, add a cycle or so for misaligned buffers.

The Linux TCPIP code is quite similar, except for using unrolling which simplifies the scheduling quite a bit.

Terje

--
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"almost all programming can be viewed as an exercise in caching"

+--------------- | Rob Warnock wrote: | > The Am29000 RISC CPU's "EXTRACT" instruction (circa 1984) did | > precisely this, except for 32 bits instead of 16. The amount | > of the shift was set in a separate small control register, | > and EXTRACT specified the two input & one output registers. | > | > You could do a really cool word-at-a-time non-aligned "memcpy()"... | > "memcpy_and_IP_checksum()" in only one clock cycle/byte (asymptotic). | | I assume it was mostly used to byte-align data? Arbitrary bit alignment | for source packets seems quite unlikely. :-) +---------------

Quite true, for networking. But the AMD-provided BITBLT graphics library primitives for the 29k *did* do arbitrary bit re-alignment memory-to memory copies using unrolled LOADM/EXTRACT*n/STOREM loops. [Since the 29k ended up being used a lot in printers, I guess that's not too surprising.]

-Rob

----- Rob Warnock

627 26th Avenue San Mateo, CA 94403 (650)572-2607