Fred Bloggs=20 I am keeping botrh timer sections for the reason that I want to have a = dark out of reset function so that The 5 hour delay starts when timer = section a comes out of reset. For example if Ralay A shuts of at 6.45PM = I want relays B to stay on exactly for exactly five hours after. To =
11:45PM. I want a exact five hour delay regardless of Relay A out of = reset on U2 U3 U4 U6 U9.
I have fixed my math error on U2 that is now 600HZ /10 giving me 60HZ. = It's output on Pin 1 not Pin 3.
Sheet A
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The 74LS273 will be on a 1HZ sample from the Q pin (Pin 1) on U13 so it = won't "freeze" when U2 U3 U4 U6 U9 are in reset when the LDR is in full = light.
Sheet B
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--=20 My cat Tigger says every morning... "Before my morning coffee... I might as well be a dog!" To contact follow the link below.
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--=20 My cat Tigger says every morning... "Before my morning coffee... I might as well be a dog!" To contact follow the link below.
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Fred Bloggs
Scott Wiper wrote: > Fred Bloggs I am keeping botrh timer sections for the reason that I > want to have a dark out of reset function so that The 5 hour delay > starts when timer section a comes out of reset. For example if Ralay > A shuts of at 6.45PM I want relays B to stay on exactly for exactly > five hours after. To 11:45PM. I want a exact five hour delay > regardless of Relay A out of reset on U2 U3 U4 U6 U9.
I understand that- so let's say you have a single 1Hz counter chain that runs continuously -always sampling the comparator outputs. When the circuit is in the LIGHT state then:
1) enable the 1 second pulses to the totalizer ( at 6 minute = 1/10th hour rate?)
2) activate RLY DRVR A
3) activate RLY DRVR B
4) hold this state indefinitely until LIGHT-to-DARK transition
While in the LIGHT state, IF the LDR comparator indicates a LIGHT-to-DARK transition, then:
1) enable the 120 second counter, no other signal changes made
2) wait for 120s timeout and RST 120 second counter on any DARK-to-LIGHT transition of LDR
3) IF LDR remains DARK throughout 120 second interval then put circuit in DARK state ELSE circuit remains in LIGHT state
The circuit in DARK state for less than 5 hours is:
1) 1 second pulses to totalizer remain enabled
2) RLY DRVR A is OFF
3) RLY DRVR B is ON
4) 5 HOUR timer is taken out of RST and allowed to count
5) Hold this state until the sooner of 5.1) LDR indicates DARK-to-LIGHT transition after passing 120 second timeout test, or 5.2) 5 HOUR timer indicates 5 hour mark has been reached.
The circuit is in DARK state > 5 hours, then:
1) 1 second pulses to totalizer disabled
2) RLY DRVR A is OFF
3) RLY DRVR B is OFF
4) circuit remains in this state until LDR DARK-to-LIGHT transition passes 120 second timeout test.
Your U4/U5 will not work: U5 goes HIGH in U4 states
60,61,62,63,124,125,126,127 which translate in time to pulses at times
1.0s, 2.07s, 3.11s, 4.18s...etc- so this needs to be fixed. Then U6/U5 are labeled divide by 120 when this is a divide by 60, and this divider has the same problem as noted with U4/U5. There is no delay at all on the comparator outputs- this is not good. Also the RLY DRV A will have trouble driving the CMOS 4071 and ULN2003 HIGH at the same time- you can change this like so: Please view in a fixed-width font such as Courier.
Sheet B is very good- use this as an example of how to fix the counters on sheet A.
S
Scott Wiper
Scott Wiper wrote: I have made some changes on RLY DRVR A (PIN 2 U8) and RLY DRVR B (PIN 5 = U8). You will notice the changes on sheet A. This inclucdes U4/U5 and = U6/U5. I have fixed the other problem with the 4071 by using D3 and Q3 on the = LS273
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While in the LIGHT state, IF the LDR comparator indicates a=20 LIGHT-to-DARK transition, then:
1) enable the 120 second counter, no other signal changes made
2) wait for 120s timeout and RST 120 second counter on any DARK-to-LIGHT =
transition of LDR
3) IF LDR remains DARK throughout 120 second interval then put circuit=20 in DARK state ELSE circuit remains in LIGHT state
All of the chnages as you descirbed have been made on sheet C. U19 on = sheet C can be tied back to the MASTER RESET. Keeping both timer = sections (A and B) in the light state or the dark state. In the light = state the totaliser will be advanced on counter section B. The counter = section A will be held in reset intil transition. This a achieved on U19 = and U20 tying PIN 1 to PIN 13 so there is a 120 second hold until reset. = I cheated a bit here by taking the 1HZ and using U17 as devide by two = function.
You see it here. =20
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The circuit in DARK state for less than 5 hours is:
1) 1 second pulses to totalizer remain enabled
2) RLY DRVR A is OFF
3) RLY DRVR B is ON
4) 5 HOUR timer is taken out of RST and allowed to count
5) Hold this state until the sooner of 5.1) LDR indicates DARK-to-LIGHT=20 transition after passing 120 second timeout test, or 5.2) 5 HOUR timer=20 indicates 5 hour mark has been reached.
The circuit is in DARK state > 5 hours, then:
1) 1 second pulses to totalizer disabled
2) RLY DRVR A is OFF
3) RLY DRVR B is OFF
4) circuit remains in this state until LDR DARK-to-LIGHT transition=20 passes 120 second timeout test.
I have done this by ORing the two outputs from U8 and inverting this = signal to U12's rest input. So when in light state reset on counter = section B is held low enabling the count to the totaliser. Even when = RELAY B is in timeout. After the delay cycle the inverter will place a = high signal on the reset stopping the count and disabling the totaliser, = But counter section A continues to until DARK to LIGHT transition.
Here at
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Keep plugging at this.
Oh I am still plugging at it. I am begining to grasp what you are = saying. Can you look at this design.
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Fred Bloggs
Scott Wiper wrote: > "Fred Bloggs" wrote in message > news: snipped-for-privacy@nospam.com... >
I am still finding errors in the divide ratios and interconnections, with some counters unconnected. Below I have drawn three essential counter types that the controller requires, and this includes the good one you have been using. Try to draw up a Sheet D that shows the overall circuit operation controlling your counters using the "high level" blocks given. I have provided an example below with a single 1Hz clock source that is sufficient for your purposes- you do not require two 1Hz sources- you are using many more counters than you need, and you do not require a single CD4017. Your Sheet D should show the counter TYPE blocks and how your external signals like the LDR comparator go into controlling various RST lines. Please view in a fixed-width font such as Courier.
BACKGROUND COUNTER TYPES
TYPE 1 This counter divides input frequency by N and outputs a pulse of duration equal to CK IN '0' time. This counter is used through- out existing arrangement. CD4024 -or- CD4040 -or- CD4020 +-----+ 1/2 | CTR | CD4082 | |---|__ | |---| \ G1 | N | | >----------+ CK | |---|__/ | 1/2 IN | |---| | CD4013 >-+--o>CK | +-------+ | | | | S | CLKOUT | | | +---|D Q|-+--->