Virtex6HXT PCIe 8X Gen2 timing closure problem

I'm having a terrible time getting the V6 PCIe core to consistently meet timing, it works occasionally but usually it misses. I've used the suggested constraints that Coregen puts out but that doesn't seem to be sufficient. There is a 500MHz section in the Xilinx core which is the source of the problems. Has anyone been able to get it to place and route reliably? Is there an area constraint for the 500MHz section or some specific flip flop placements that would help?