Spartan 3A startup

OOps, I think I found at least the first goof. I forgot to hook up VCCAUX! I thought it was for special voltage output drivers, but not so.

Jon

Ah, that helped a lot! Next problem turned out to be that the bit ordering of an MCS file is reversed for Xilinx or SPI EPROM chips in the file. When I selected the PROM formatter to make Xilinx EPROM files instead of SPI, the FPGA accepted the configuration. It now is doing things that look right on a scope, but it doesn't seem to be communicating with the test computer. I'll probably have to hook up the logic analyzer to see where it is going wrong.

Jon

Even before reading your next post I suspected a power issue. Also INIT_B should be pulled up. If it has an internal pullup, that might be OK, but the configuration process will be delayed if INIT_B stays low after releasing PROGRAM_B, so I usually add an external pullup anyway.

-- Gabor

Yes, this once per second pulsing really had to be either power or some floating pin. I'm pretty sure INIT_B does have internal pullup, but I'll double check the docs. Extra-fast config is not required, here, it just needs to be finished before the PC boots.

Anyway, found another goof, I had failed to solder one whole row of pins on one of the voltage translator chips! Now the board is communicating with the PC, and some preliminary tests all look OK. I couldn't figure out how it could have been so far off, as the VHDL is almost identical to the Spartan 2E version. The UCF pad assignment was the only real change, so I was looking for a mis-assignment of one wrong pin and not thinking as globally as I should have.

Jon