Greetings all,
Further to previous thread(s), has anyone here experience in setting up a linting tool such as Spyglass or LEDA? How long did it take?
My thoughts are that a suite of test-case files is needed to test for detection of each code breach, and that preparing that would take a week or
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Setup can be very simple. Most tools use the same command line syntax as verilog so all you have to do is configure your code for synthesizable only
and remove all the bus functional models from your testbench.
You only need a suite if you have multiple configurations to test. One test
checks for all violations in the same pass.
John Eaton
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A clarification. My intention is to test the tool(s), to check whether they find the rule breaches correctly...
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How long it will take to test the linting tool depends entirely on the number and complexity of the rules you are trying to enforce.
If you have half a dozen simple rules, a couple of weeks is probably plenty of time. If you have a hundred rules, many of which are rather complex, two months might not be enough time.
What code language are you wanting to lint, VHDL or Verilog?
What kind of policies are you trying to enforce? Hazardous, frequently misused or mistake-prone usage? Maintainability guidelines (e.g. unused declarations)? Local style guide?
Andy
number and complexity of the rules you are trying to enforce.
plenty of time. If you have a hundred rules, many of which are rather complex, two months might not be enough time.
misused or mistake-prone usage? Maintainability guidelines (e.g. unused declarations)? Local style guide?
VHDL.
All of the above for preference. We have many rules. Precise number subject to next week's document review.
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Why do you want to write tests for a linting tool, is this a DO-254 requirement?
There is no question that a static/dynamic linting tool will have a positive impact on your development, it all comes down to your EDA budget and not on the tools usefulness.
I would get some evaluation licenses and simply run them on all your previous designs. All linting tools are push-button with a standard set of rules (DO-254, RMM, Best Design Practise, Xilinx, Altera etc) so it shouldn't take too long to get some results. I am sure that analysing these results will highlight some interesting coding issues (and the usual bunch of false positives). It is a bit like running Code Coverage for the first time on your design. Then during the project work on creating/improving your own ruleset.
If you are doing an FPGA design then I would probably go for Mentor's DesignChecker or Aldec's Alint rather than Spyglass which is mainly an ASIC tool and hence might be limited in their VHDL support.
Good luck,
Hans
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